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The role of long and short paths in circuit performance optimization
1994
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. ...
To bring in the timing of the circuit, we make use of a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. ...
#(GLs) is the number of gates covered by long and short paths. #(GL.s.) is the number of gates covered by long and short destabilizing paths. ...
doi:10.1109/43.293942
fatcat:2rntdnokg5cgpb6ta6u6ytkm6a
The role of long and short paths in circuit performance optimization
[1992] Proceedings 29th ACM/IEEE Design Automation Conference
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We consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. ...
To bring in the timing of the circuit, we make use of a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. ...
#(GLs) is the number of gates covered by long and short paths. #(GL.s.) is the number of gates covered by long and short destabilizing paths. ...
doi:10.1109/dac.1992.227745
fatcat:zkhjecvw5rfbdaafq62vdcojoe
Managing contamination delay to improve Timing Speculation architectures
2016
PeerJ Computer Science
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In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. ...
We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact. ...
The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. ...
doi:10.7717/peerj-cs.79
fatcat:x2cds3ygv5h3zccalqlbdufgry
The amorphous FPGA architecture
2008
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08
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It is shown that, on average, an FPGA with the amorphous architecture can achieve a 1.35 times improvement in logic density, 9% improvement in average net delay, and 4% improvement in the critical-path ...
Designed for high performance, routability, and ease-of-use, it supports variablegranularity logic blocks, dedicated wide multiplexers, and variable-length bypassing interconnects with a symmetrical structure ...
Wenyi Feng from Actel for the addition of several key references. ...
doi:10.1145/1344671.1344700
dblp:conf/fpga/Lin08
fatcat:bab2pkdhozaozbyci3u6ji36hi
Ant Colony Optimization for Dynamic Routing in Wireless Computer Networks for Improvement in Quality of Services
2013
International Journal of Computer Applications
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Ant Colony Optimization (ACO) and in the case of well implemented ACO techniques, optimal performance is comparative to existing top-performing routing algorithms. ...
Such a research has yielded ways to minimize the number of nodes that are taken to get to the destination, techniques for quickly resolving an efficient path, and ways to avoid having loops within a routing ...
As a result, the quantity of pheromone is left with higher speed in short side than long side because more ants choose short side than long side. ...
doi:10.5120/11960-7799
fatcat:3xawsbundzgavou6nsavk3abki
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters
2002
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Trends in CMOS technology and VLSI architectures are causing interconnect to play an increasing role in overall performance, power consumption and design e ort. ...
This paper presents a new circuit called a booster which compares favorably with repeaters in terms of area, performance, power and placement s e n s itivity. ...
Short-circuit power dissipation for the paths between V dd and Vss through transistors (5, 6, 7, 8) and (9, 10) is negligible, since the transistors are of smaller size and for both of these paths, input ...
doi:10.1109/43.974137
fatcat:spvkiruv7nb43pxh5x3dxeujzu
Boosters for driving long on-chip interconnects
2001
Proceedings of the 2001 international symposium on Physical design - ISPD '01
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Trends in CMOS technology and VLSI architectures are causing interconnect to play an increasing role in overall performance, power consumption and design e ort. ...
This paper presents a new circuit called a booster which compares favorably with repeaters in terms of area, performance, power and placement s e n s itivity. ...
Short-circuit power dissipation for the paths between V dd and Vss through transistors (5, 6, 7, 8) and (9, 10) is negligible, since the transistors are of smaller size and for both of these paths, input ...
doi:10.1145/369691.369775
dblp:conf/ispd/NalamalpuB01
fatcat:6c4uk77vxrf2jhcnog5gkzxeqe
A novel methodology for speeding up IC performance in 32nm FinFET
2012
IEICE Electronics Express
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role in application-specific integration circuits in the 22 nm node and beyond. ...
In the high-speed and low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between the power consumption and high performance which play an important ...
Acknowledgments This work was supported by the 2009 Research Fund of the UNIST (Ulsan National Institute of Science and Technology). This work also was partially sponsored by NRF grant #2010-0012867. ...
doi:10.1587/elex.9.227
fatcat:inj62fb4iva2vgcyaeocty5b7i
Dynamic clock-frequencies for FPGAs
2006
Microprocessors and microsystems
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Such a clocking strategy cannot take advantage of the full run-time potential of an application running on a specific device and in a specific operating environment. ...
We then present a framework for exploring the dynamic behaviour of suitable clock-frequencies for a number of FPGA applications in varied operational environments. ...
over short periods of time, • The effect of different environments on the optimal clock-frequency. ...
doi:10.1016/j.micpro.2006.02.006
fatcat:3w2co4775fdche7hmwdmn47bpq
Crosstalk noise reduction in synthesized digital logic circuits
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. ...
The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. ...
This observation has been made by [22] , who emphasized the role of driver strength in noise calculations, and suggested to perform track assignments in channel routing by sorting nets according to the ...
doi:10.1109/tvlsi.2003.817551
fatcat:a6ysah3hxjdfbckanu3gyrviqi
On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor
2015
IEICE Electronics Express
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In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role ...
The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. ...
The dynamic threshold voltage change in the IGAA transistors can provide additional options for circuit designers in terms of performance and power optimization according to the requirements of the integrated ...
doi:10.1587/elex.12.20150321
fatcat:iyre4hsi3vbstkxvnesj7c4eha
Incorporating interconnect, register, and clock distribution delays into the retiming process
1997
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Friedman is a member of the editorial board of Analog Integrated Circuits and Signal Processing, Chair of the VLSI Systems and Applications CAS Technical Committee, Chair of the VLSI track for ISCAS '96 ...
The approach used in the proposed algorithm is to initialize these ranges with unbounded values and to continuously tighten these ranges using localized timing constraints until an optimal solution is ...
The first two authors of this paper would like to specifically acknowledge the insightful and important contributions of the third author and their mentor and friend, Dr. James H. ...
doi:10.1109/43.559335
fatcat:n6d5jh5jvnek7c3qpgohtzuwk4
DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design
2006
Proceedings of the Design Automation & Test in Europe Conference
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In the
essential role for robustness and performance of second step the circuit will be optimized for nominal
integrated circuits. ...
Within this step sensitivities of the
account when adjusting the values for the design circuit performances depending on design parameter
parameters in order to ensure the functionality of the ...
doi:10.1109/date.2006.243763
dblp:conf/date/BuhlerKBHSSPR06
fatcat:pu7a6zbvsjecvledk7up5ns5pm
The role of custom design in ASIC Chips
2000
Proceedings of the 37th conference on Design automation - DAC '00
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Routing the wires first gives early visibility of timing issues, allows the design to be optimized to drive the exact wire load, and enables the use of fast circuit styles. ...
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. ...
Structured layout enables the use of fast circuits Fast circuits, such as domino logic, and low-swing high fan-in and fan-out circuits get much of the credit for the performance and power advantages of ...
doi:10.1145/337292.337604
dblp:conf/dac/DallyC00
fatcat:pfx6dsagdjdnno2hzbdpkgxrjm
Modified Relay Selection and Circuit Selection for Faster Tor
[article]
2018
arXiv
pre-print
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In this paper, we examine both the process of selecting among pre-built circuits and the process of selecting the path of relays for use in building new circuits to improve performance while maintaining ...
Users of the Tor anonymity system suffer from lessthan- ideal performance, in part because circuit building and selection processes are not tuned for speed. ...
This greedy approach may miss the optimal path, for some definition of optimal, but our design aims to select from a wide range of paths with good performance and to avoid poorly performing paths. ...
arXiv:1608.07343v3
fatcat:k4igrobktzhypkp55ukcjt3lea
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