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Page 5180 of Mathematical Reviews Vol. , Issue 96i [page]

1996 Mathematical Reviews  
(J-GUN-C; Kiryu); Shibata, Yukio (J-GUN-C; Kiryu) The number of labeled graphs placeable by a given permutation.  ...  Using newly introduced generalizations of Fibonacci and Lucas numbers, the authors count the number of labeled graphs which are m-placeable by a given permutation.  ... 

Page 54 of Mathematical Reviews Vol. , Issue 94a [page]

1994 Mathematical Reviews  
Summary: “Graphs on alphabets are constructed by labelling the vertices with words on a given alphabet, and specifying a rule that relates pairs of different words to define the edges.  ...  Summary: “Two related concepts are studied: the decomposition of graphs into edge disjoint cliques of either given or arbitrary order, and the number of edge disjoint cliques of given order.  ... 

Packing a number of copies of a (p, q)-graph [article]

Yun Wang, Jin Yan
2020 arXiv   pre-print
A graph G with order n is said to be k-placeable if there are k edge disjoint copies of G in the complete graph on n vertices. A (p, q)-graph is a graph of order p with q edges.  ...  Motivated by their results, this paper characterizes (n, n-1)-graphs with girth at least 9 which are 4-placeable. We also consider the k-placeable of (n, n+1)-graphs and 2-factors.  ...  Acknowledgments We are very grateful to the referees for their many valuable suggestions and comments, which make the proof much simpler and clearer.  ... 
arXiv:2002.01266v2 fatcat:e44gpn5kgbd3dd32xhbp6banoy

Labeled packings of graphs

Éric Duchêne, Hamamache Kheddouci, Richard J. Nowakowski, Mohammed Amin Tahraoui
2013 The Australasian Journal of Combinatorics  
Graph packing generally considers unlabeled graphs. In this paper, we introduce a new variant of the graph packing problem, called the labeled packing of graphs.  ...  Hence, we can say that the labeled embedding number of G denotes the maximum number of cycles induced by a permutation of G.  ...  Two studies are possible for the labeled graph packing problem: (i) packing important number of sample graphs (or copies of a given graph) in a complete graph; or (ii) packing a fixed number (usually two  ... 
dblp:journals/ajc/DucheneKNT13 fatcat:4zdhn7wxirdjzgygj2pssxtfsa

Neural Logic Machines [article]

Honghua Dong, Jiayuan Mao, Tian Lin, Chong Wang, Lihong Li, Denny Zhou
2019 arXiv   pre-print
In our experiments, NLMs achieve perfect generalization in a number of tasks, from relational reasoning tasks on the family tree and general graphs, to decision making tasks including sorting arrays, finding  ...  NLMs exploit the power of both neural networks---as function approximators, and logic programming---as a symbolic processor for objects with properties, relations, logic connectives, and quantifiers.  ...  ACKNOWLEDGEMENTS We thank Rishabh Singh, Thomas Walsh, the area chair, and anonymous reviewers for their insightful comments.  ... 
arXiv:1904.11694v1 fatcat:6umfj3sbubcgfiputfxf6urn5i

Symmetry within the sequence-pair representation in the context of placement for analog design

F. Balasa, K. Lampaert
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
), can be easily handled by employing the sequence-pair representation.  ...  a more recent topological representation called sequence-pair [14], which has the advantage of not being restricted to slicing floorplan topologies.  ...  time, where is the number of placeable cells.  ... 
doi:10.1109/43.851988 fatcat:ugifujuoqfhavj7avzttnwhlaq

APlace: A High Quality, Large-Scale Analytical Placer [chapter]

Andrew B. Kahng, Sherief Reda, Qinke Wang
2007 Series on Integrated Circuits and Systems  
We also provide extensive experimental results on a number of benchmark sets, including the IBM ISPD'04, IBM-PLACE 2.0, ICCAD'04, ISPD'05, PEKO'05, ISPD'06, PEKO'06 as well as using the zero-change netlist  ...  With these complexities in mind, placers are faced with the burden of finding an arrangement of placeable objects under strict wirelength, timing, and power constraints.  ...  Clustering reduces the number of placeable objects and thus speeds up the calculation of density penalty.  ... 
doi:10.1007/978-0-387-68739-1_7 fatcat:m4e4otw6zrd6ncclryxu3io76m

Transistor placement for noncomplementary digital VLSI cell synthesis

Michael A. Riepe, Karem A. Sakallah
2003 ACM Transactions on Design Automation of Electronic Systems  
We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains.  ...  In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts.  ...  ACKNOWLEDGMENTS The authors would like to thank Professor Rob Rutenbar and Dr. Phiroze Parakh for many interesting discussions, and the anonymous reviewers for their helpful suggestions.  ... 
doi:10.1145/606603.606608 fatcat:rnc3wsgs2jc3hmxi6jsbywth2e

A robust detailed placement for mixed-size IC designs

Jason Cong, Min Xie
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
Furthermore, XDP displays a higher robustness than the other tools by covering a broader spectrum of examples by different global placement tools.  ...  In this paper we propose a three-step approach, named XDP, for mixed-size detailed placement. First, a combination of constraint graph and linear programming is used to legalize macros.  ...  The placeable objects are examined one at a time.  ... 
doi:10.1145/1118299.1118353 fatcat:v4fk5ru5kfa6vews34ux733rne

Fast compilation for pipelined reconfigurable fabrics

Mihai Budiu, Seth Copen Goldstein
1999 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99  
The key behind our approach is that we never backtrack, rip-up, or re-route. Instead, the graph representing the computation is preprocessed to guarantee routability by inserting lazy noops.  ...  The core of the compiler is a linear time place and route algorithm more than two orders of magnitude faster than traditional CAD tools.  ...  We offer a special thanks to Srihari for his contribution to the compiler. This work is supported in part by a grant from Altera Corporation and DARPA contract No. DABT63-96-C-083.  ... 
doi:10.1145/296399.296459 dblp:conf/fpga/BudiuG99 fatcat:7aqj7xbewjhovluhcmyqz4kjie

Smart Variations: Functional Substructures for Part Compatibility

Youyi Zheng, Daniel Cohen-Or, Niloy J. Mitra
2013 Computer graphics forum (Print)  
We demonstrate that starting even from a small set of models such a simple geometric approach can produce a diverse set of non-trivial and plausible model variations.  ...  Hence, the user has to manually ensure that the final model remains functionally valid.  ...  The work was partially supported by the Marie Curie Career Integration Grant 303541.  ... 
doi:10.1111/cgf.12039 fatcat:sziuffaerbf5hi7qkp7ximnvu4

PADE

Samuel Ward, Duo Ding, David Z. Pan
2012 Proceedings of the 49th Annual Design Automation Conference on - DAC '12  
To the best of our knowledge, this is the first attempt to link data learning, datapath extraction with evaluation, and placement and has the tremendous potential for pushing placement state-of-the-art  ...  This work presents PADE, a new placer with automatic datapath extraction and evaluation.  ...  Automorphism Group: The set of automorphisms of a given graph forms the automorphism group of the graph and is denoted by Aut(G).  ... 
doi:10.1145/2228360.2228497 dblp:conf/dac/WardDP12 fatcat:xilgxaryzvetvc6wd3jptaq2ta

Automatic validation of requirements to support multidimensional design

Oscar Romero, Alberto Abelló
2010 Data & Knowledge Engineering  
(a detailed list of the main advantages of MDBE over previous approaches is given in Section 2).  ...  already queried by the user.  ...  Acknowledgments This work has been partly supported by the Ministerio de Ciencia e Innovación under project TIN2008-03863.  ... 
doi:10.1016/j.datak.2010.03.006 fatcat:n77rttp2djbfzldc7bg34tf4em

On sampling graphical Markov models [article]

Megan Bernstein, Prasad Tetali
2017 arXiv   pre-print
We also investigate the ratio of Markov equivalence classes to DAGs and a Markov chain of He, Jia, and Yu for random sampling of sparse Markov equivalence classes.  ...  We create and analyze a Markov chain for uniform random sampling on the DAGs inside a Markov equivalence class.  ...  We thank Caroline Uhler and Liam Solus for several helpful discussions on the topic of enumeration of Markov equivalence graphs.  ... 
arXiv:1705.09717v2 fatcat:y5itywnolzd5flufdkmezm7jkm

Integrated logic synthesis using simulated annealing

Petra Färm, Elena Dubrova, Andreas Kuehlmann
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices.  ...  Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels.  ...  The number of levels in the graph is given by the latest arrival time at the primary outputs, max ∀u∈PO (l a (u)).  ... 
doi:10.1145/1973009.1973095 dblp:conf/glvlsi/FarmDK11 fatcat:dlju72re25ae7jgninv5kuntia
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