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The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor

S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, M. Horowitz
2006 IEEE Journal of Solid-State Circuits  
The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation.  ...  The final aspect of circuit design improvement involved the I/O design for our legacy multi-drop system bus.  ...  ACKNOWLEDGMENT The authors recognize the extraordinary efforts of a committed design team in making the Montecito processor a success.  ... 
doi:10.1109/jssc.2005.859894 fatcat:nkeithu33rhjpao3xqcnmmgzg4

The implementation of a 2-core multi-threaded itanium-family processor

S. Naffziger, B. Stackhouse, T. Grutkowski
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.  
The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation.  ...  The final aspect of circuit design improvement involved the I/O design for our legacy multi-drop system bus.  ...  ACKNOWLEDGMENT The authors recognize the extraordinary efforts of a committed design team in making the Montecito processor a success.  ... 
doi:10.1109/isscc.2005.1493929 fatcat:ssq5v5vcwbak3ackojzzrbqe4y

Implementation and evaluation of a microthread architecture

K. Bousias, L. Guang, C.R. Jesshope, M. Lankamp
2009 Journal of systems architecture  
It is implemented here in the instruction set of a dynamically scheduled RISC processor and many such processors form a microgrid.  ...  This paper introduces the model, the processor and chip architecture and its emulation on a range of computational kernels.  ...  Organisation) for its funding of the project "Microgrids".  ... 
doi:10.1016/j.sysarc.2008.07.001 fatcat:44uq6mcpuzgnvn56svsa73jbnu

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 SIGARCH Computer Architecture News  
On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads,  ...  The concept of VMT is prototyped on an Itanium r 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors.  ...  We would also like to thank Hank Levy for his valuable suggestions for improving the quality of this paper; and Ryan Rakvic, Natalie Enright, and Jeff Brown for further editing comments.  ... 
doi:10.1145/1037947.1024411 fatcat:7m34jxhc7vfpvfia4r5o4pdpoe

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 ACM SIGOPS Operating Systems Review  
On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads,  ...  The concept of VMT is prototyped on an Itanium r 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors.  ...  We would also like to thank Hank Levy for his valuable suggestions for improving the quality of this paper; and Ryan Rakvic, Natalie Enright, and Jeff Brown for further editing comments.  ... 
doi:10.1145/1037949.1024411 fatcat:bcmhsxjs4zfixl62fx5mxxcitq

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 Proceedings of the 11th international conference on Architectural support for programming languages and operating systems - ASPLOS-XI  
On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads,  ...  The concept of VMT is prototyped on an Itanium r 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors.  ...  We would also like to thank Hank Levy for his valuable suggestions for improving the quality of this paper; and Ryan Rakvic, Natalie Enright, and Jeff Brown for further editing comments.  ... 
doi:10.1145/1024393.1024411 dblp:conf/asplos/WangCWKGCYSMS04 fatcat:gcd6gtgt7vgbzfdphpfpme6g6i

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

Perry H. Wang, John P. Shen, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore
2004 SIGPLAN notices  
On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads,  ...  The concept of VMT is prototyped on an Itanium r 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors.  ...  We would also like to thank Hank Levy for his valuable suggestions for improving the quality of this paper; and Ryan Rakvic, Natalie Enright, and Jeff Brown for further editing comments.  ... 
doi:10.1145/1037187.1024411 fatcat:frntjetjcvbadehs5j5et5lcgu

Speculative precomputation

Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen
2001 Proceedings of the 28th annual international symposium on Computer architecture - ISCA '01  
This technique is evaluated by simulating the performance of a research processor based on the Itanium T M ISA supporting Simultaneous Multithreading.  ...  This paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications.  ...  Additionally, we would like to thank the many referees of the previous versions of this paper for their extremely useful suggestions.  ... 
doi:10.1145/379240.379248 dblp:conf/isca/CollinsWTHLLS01 fatcat:6ickmrby6nbkbpauxi4lrqpqqy

Speculative precomputation

Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen
2001 SIGARCH Computer Architecture News  
This technique is evaluated by simulating the performance of a research processor based on the Itanium T M ISA supporting Simultaneous Multithreading.  ...  This paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications.  ...  Additionally, we would like to thank the many referees of the previous versions of this paper for their extremely useful suggestions.  ... 
doi:10.1145/384285.379248 fatcat:o3vjjy5775azpa6l2gqfzrqpaa

Parallelism via Multithreaded and Multicore CPUs

A.C. Sodan, J. Machina, A. Deshmeh, K. Macnaughton, B. Esbaugh
2010 Computer  
However, only 25% of the additional chip space that became available per year was actually harvested by new architectural features. 2 Additionally, the performance gap between processors and memory limits  ...  Moore's Law, which projects that the density of circuits on chip will double every eighteen months, still applies and is providing hardware designers with the ability to add more complexity to a chip.  ...  Acknowledgments We thank (alphabetically) Tracy Carver of AMD, Jaime Moreno of IBM, Denis Sheahan of Sun, and Xinmin Tian of Intel for their helpful feedback and for validation of our CPU/GPU data.  ... 
doi:10.1109/mc.2010.75 fatcat:z34ptnd3rbgdvf7md5dmmqinfm

Parallel versions of FORM and more [article]

Matthias Steinhauser, Takahiro Ueda, Jos A.M. Vermaseren
2015 arXiv   pre-print
In particular, we provide a brief overview about the historical developments, discuss the strengths of ParFORM and TFORM, and mention typical applications.  ...  We review the status of the parallel versions of the computer algebra system FORM.  ...  We acknowledge the use of the High Performance Computing Center Stuttgart (HLRS) where part of the calculations connected to FIESTA have been carried out.  ... 
arXiv:1501.07119v1 fatcat:iubyit5bnzbtjlevvxv6xl7ow4

Modeling Heterogeneous Mesoscopic Fluids in Irregular Geometries using Shared Memory Systems

Krzysztof Boryczko, Witold Dzwinel, David A. Yuen
2005 Molecular Simulation  
The particle code was tested on 4 and 8 processors of SGI/Origin 3800 (R14000/500), IBM Regatta (Power4/1300), SGI Altix 3000 (Itanium®2/1300) systems and two-processor AMD Opteron 240 motherboard.  ...  We show that irregular boundary conditions and heterogeneity of the particle fluid inhibit efficient implementation of the model on superscalar processors.  ...  Acknowledgements Support for this work has come from the Polish Committee for Scientific Research (KBN) project 4T11F02022 and the Complex Fluids Program of DOE.  ... 
doi:10.1080/08927020412331299341 fatcat:fbf5o2bof5guzbywusayvo3rmm

Processing-in-memory technology for knowledge discovery algorithms

Jafar Adibi, Tim Barrett, Spundun Bhatt, Hans Chalupsky, Jacqueline Chame, Mary Hall
2006 Proceedings of the 2nd international workshop on Data management on new hardware - DaMoN '06  
Measured speedups of 8x are shown on two additional bandwidth benchmarks, even though the Itanium-2 has a clock rate 6X faster.  ...  PIM chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth  ...  Future devices will have denser memories and multi-core processors, not higher clock speeds or more complex processors.  ... 
doi:10.1145/1140402.1140405 dblp:conf/damon/AdibiBBCCH06 fatcat:2vv4tnhq2fb6zj3snfkh2dfg64

Advances in computer architecture [article]

Irfan Uddin
2013 arXiv   pre-print
In the past, efforts were taken to improve the performance of a processor via frequency scaling.  ...  However, industry has reached the limits of increasing the frequency and therefore concurrent execution of instructions on multiple cores seems the only possible option.  ...  Each core implements the concurrency constructs in its instruction set and is able to support hundreds of threads and their contexts, called microthreads and tens of families (i.e. ordered collections  ... 
arXiv:1309.5459v1 fatcat:3ry6sbh6xncdrmhzbpordmxexi

Architecture and Implementation of a Reduced EPIC Processor

Jun GAO, Minxuan ZHANG, Zuocheng XING, Chaochao FENG
2013 IEICE transactions on information and systems  
The die size of the REPICP is 100 mm 2 (10 × 10), and consumes only 12 W power when running at 300 MHz. key words: ILP, EPIC, IA-64, processor architecture, hardware implementation  ...  This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor.  ...  Acknowledgments The authors acknowledge the contributions from the entire REPICP research team. This work is partially supported by national 863 plans projects under Grant  ... 
doi:10.1587/transinf.e96.d.9 fatcat:66x2fqheznbute67efkbz3sat4
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