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Process Variations and Process-Tolerant Design

Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
To deal with increasing parameter variations, it is important to accurately model the impact of device parameter variations at circuit level and develop process-tolerant design techniques for both logic  ...  This article analyzes the impact of process parameter variations on logic circuits and memory and focuses on some major works in the area of process-tolerant design methodology at circuiffarchitecture  ...  Increasing variations (both inter-die and intra-die) in device .., and interconnect parameters (channel length, gate width, oxide thickness, device threshold voltage etc.) produce large spread in the speed  ... 
doi:10.1109/vlsid.2007.131 dblp:conf/vlsid/BhuniaMR07 fatcat:haw2cidqhng7ngucgvwiftnsza

Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

Marco Lanuzza, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2011 Journal of Low Power Electronics and Applications  
In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits.  ...  Energy consumption is one of the main barriers to current high-performance designs.  ...  It was shown that the impact of intra-die PVs on timing yield strongly depends on the considered logic architecture and chosen power supply voltage.  ... 
doi:10.3390/jlpea1010097 fatcat:tmw7wwmghbbzdgsn7n5f55eeei

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions

Swarup Bhunia, Kaushik Roy
2007 2007 IEEE International Test Conference  
On the other hand, variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage, leading to loss in parametric yield.  ...  Hence, there is a need to consider test and yield, while designing for low-power and robustness under variations.  ...  An investigation was performed in [33] to observe the impact of body biasing on delay fault test under both inter and intra-die process variations.  ... 
doi:10.1109/test.2007.4437659 dblp:conf/itc/BhuniaR07 fatcat:bdsfonjkkrhnxeigu3gog4y6de

A 45.6μ213.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS

Basab Datta, Wayne Burleson
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
The increased susceptibility of circuit performance characteristics to parameter variations in deep sub-micron technologies motivates the need for low-overhead (area/power) and high-sensitivity process  ...  The design is robust towards temperature variations and supply induced noise incurring an accuracy loss of 5mV (worst-case) and 4mV (1-σ) respectively of the NMOS threshold-voltage.  ...  Intra-die threshold variations have been shown to adversely influence path-delays of low-voltage digital circuits [2] and consequently, cause glitches and clock-skew.  ... 
doi:10.1145/1973009.1973037 dblp:conf/glvlsi/DattaB11 fatcat:rgc5llk26jcdjltwfztv6gdk2y

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width

K Kunaparaju, S Narasimhan, S Bhunia
2011 2011 24th Internatioal Conference on VLSI Design  
Intra-die or within-die variations: Intra-die variations are the variations in device features that are present within a single chip, meaning that a device feature varies between different locations on  ...  The impact of within-die variation, which causes differences in path delays fabricated on the same die, is heavily influenced by circuit optimization decisions such as transistor sizing, threshold voltage  ...  IMPLEMENTATION OF VAROT ON FIR In this chapter we present the implementation of the proposed methodology on Finite Impulse Response(FIR).  ... 
doi:10.1109/vlsid.2011.58 dblp:conf/vlsid/KunaparajuNB11 fatcat:lyjvho7l7zct7fd36gfucaztzy

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

Georgios Karakonstantis, Abhijit Chatterjee, Kaushik Roy
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today.  ...  Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased  ...  ACKNOWLEDGMENT The authors would like to thank S. Ghosh, D. Mohapatra, V. Natarajan, S. Sen, and S. Devarakond for their contributions to the work discussed in Sections III and IV.  ... 
doi:10.1109/jetcas.2011.2135590 fatcat:3tnl6lww3jesfmv5ptqgpv45le

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Yusuke TSUGITA, Ken UENO, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA
2010 IEICE transactions on electronics  
An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed.  ...  The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.  ...  Acknowledgments This work is supported by VLSI Design and Education Cen-  ... 
doi:10.1587/transele.e93.c.835 fatcat:dhibudf2pvhkxjd6kwgnpnboou

Multivariate Adaptive Regression Splines in Standard Cell Characterization for Nanometer Technology in Semiconductor [chapter]

Taizhi Liu
2018 Topics in Splines and Applications  
The standard cell library provides a way for designers to place cells in rows, and it enables the automated layout generations for digital ASICs.  ...  Propagation delay is important because it has a direct effect on the speed at which a digital device, such as a computer, can operate. This is true of memory chips as well as microprocessors.  ...  For channel lengths, we have considered interdie and intra-die variation, and for threshold voltage, intra-gate variation is considered.  ... 
doi:10.5772/intechopen.74854 fatcat:gdeogvgtpvdszoywetpwxao6ou

High-performance bridge-style full adder structure

Omid Kavehei, Said F. Al-Sarawi, Derek Abbott, Keivan Navi, Said F. Al-Sarawi, Vijay K. Varadan, Neil Weste, Kourosh Kalantar-Zadeh
2008 Smart Structures, Devices, and Systems IV  
The performance of this adder in terms of power, delay, energy, and yield are investigated.  ...  The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.  ...  between delay and power, but also the impact of process and environmental variations on the delay-energy and parametric yield trade-off.  ... 
doi:10.1117/12.813924 fatcat:h3fubze6qnb55ort5w3f2nrf2y

Device-Aware Yield-Centric Dual-$V_{t}$ Design Under Parameter Variations in Nanoscale Technologies

A. Agarwal, Kunhyuk Kang, S. Bhunia, J.D. Gallagher, K. Roy
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we propose a device aware simultaneous sizing and dualdesign methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to  ...  Moreover, process parameter variations (and in turn variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield.  ...  that as the number of critical paths on a die increases, within-die delay variation causes both mean and standard deviation of the die frequency distribution to become smaller.  ... 
doi:10.1109/tvlsi.2007.898683 fatcat:7zgj7u5uejgf3bhavario75cci

Coping with Variations through System-Level Design

Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy
2009 2009 22nd International Conference on VLSI Design  
As the magnitude of parameter variations increases with technology scaling, these techniques are not sufficient to address the negative impact that variations have on IC performance, power, yield, and  ...  Most work on addressing variations has focused on device, circuit, and logic-level solutions.  ...  III CRITICAL PATH ISOLATION FOR TIMING ADAPTIVENESS CRISTA [20] is a new paradigm for low-power, variation-tolerant digital system design, which allows for aggressive voltage overscaling.  ... 
doi:10.1109/vlsi.design.2009.96 dblp:conf/vlsid/BanerjeeCGDRR09 fatcat:zccl2syeavdgjfrlpxjgk7cuue

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits

J. Pineda de Gyvez, H.P. Tuinhout
2004 IEEE Journal of Solid-State Circuits  
Kruseman for providing them with the experimental data on leakage current mismatch, and R. van Veen and K. van Kaam for doing the DSP leakage current measurements.  ...  ACKNOWLEDGMENT The authors would like to thank B.  ...  A statistical approach for intra-die variability for critical-path delay analysis was performed in [17] , a study of the impact of process variability on leakage current levels was done in [5] and a  ... 
doi:10.1109/jssc.2003.820873 fatcat:cwfoyj3knrezhl5zl3mfqx5vge

Leakage in nano-scale technologies

Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
We also explore process variation compensating techniques to reduce delay and leakage spread, while meeting power constraint and yield.  ...  Consequently, the identification of different leakage components is very important for estimation and reduction of leakage.  ...  This research was funded in part by SRC, DARPA-PACC, GSRC MARCO center, Intel, and IBM Corporation.  ... 
doi:10.1145/996566.996571 dblp:conf/dac/AgarwalKMR04 fatcat:vnmcqmn5wjhm3exvemcurbevqi

Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits

Joyce Kwong, Anantha P. Chandrakasan
2006 ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design  
We explore variability metrics and the variation sensitivity of stacked device topologies.  ...  We show that upsizing is necessary to achieve robustness at reduced voltages and propose a design methodology to meet yield constraints.  ...  We address inter-and intra-die variation and show that functionality in sub-threshold circuits may be compromised without proper design for variations.  ... 
doi:10.1109/lpe.2006.4271799 fatcat:xpizn24zvvhj7b3pprroo7lbxy

Variation-driven device sizing for minimum energy sub-threshold circuits

Joyce Kwong, Anantha P. Chandrakasan
2006 Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06  
We explore variability metrics and the variation sensitivity of stacked device topologies.  ...  We show that upsizing is necessary to achieve robustness at reduced voltages and propose a design methodology to meet yield constraints.  ...  We address inter-and intra-die variation and show that functionality in sub-threshold circuits may be compromised without proper design for variations.  ... 
doi:10.1145/1165573.1165578 dblp:conf/islped/KwongC06 fatcat:dujmkbzfnncp3awhs5fc2hm5zy
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