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The effect of LUT and cluster size on deep-submicron FPGA performance and density
2000
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00
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In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. ...
In particular, in the context of lookup table, cluster-based island-style FPGAs [4] we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic ...
ACKNOWLEDGMENTS The authors are grateful to Vaughn Betz and Alexander Marquardt for providing the foundation upon which this work is built, and for advice and help throughout this effort. ...
doi:10.1145/329166.329171
dblp:conf/fpga/AhmedR00
fatcat:vvvzkqslgfb7do5prbs25jrs3q
The effect of LUT and cluster size on deep-submicron FPGA performance and density
2004
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. ...
In particular, in the context of lookup table, cluster-based island-style FPGAs [4] we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic ...
ACKNOWLEDGMENTS The authors are grateful to Vaughn Betz and Alexander Marquardt for providing the foundation upon which this work is built, and for advice and help throughout this effort. ...
doi:10.1109/tvlsi.2004.824300
fatcat:rpjksdxer5crnkejdisf5awn3y
Table of contents
2004
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Ramanujam, and I. Kolcu 281 REGULAR PAPERS The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density . . . . . . . . . E. Ahmed and J. ...
Rose 288 Trading Off Transient Fault Tolerance and Power Consumption in Deep Submicron (DSM) VLSI Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
doi:10.1109/tvlsi.2004.827348
fatcat:lg6t74vs3ffi5my7oeoh7wvzva
Fine-grain leakage optimization in SRAM based FPGAs
2005
Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05
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FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. ...
We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. ...
array (2-input effective LUT size), and so on. ...
doi:10.1145/1057661.1057719
dblp:conf/glvlsi/MondalM05
fatcat:amfi6jtpb5gpfnwp52lh6nb5oq
Physical design for FPGAs
2001
Proceedings of the 2001 international symposium on Physical design - ISPD '01
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FPGAs have been growing at a rapid rate in the past few years. Their ever-increasing gate densities and performance capabilities are making them very popular in the design of digital systems. ...
In this paper we discuss the state-of-the-art in FPGA physical design. Compared to physical design in traditional ASICs, FPGAs pose a different set of requirements and challenges. ...
However, not having to account for some of these deep submicron effects simplifies not only the design cycle for FPGA users but also the development of FPGA software. ...
doi:10.1145/369691.369776
dblp:conf/ispd/Jayaraman01
fatcat:jp4epw2dcjgpbfwov76xirbmra
Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs
2012
IOSR Journal of VLSI and Signal processing
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To do the performance analysis we have implemented lookup table ( LUT) of benchmark circuit (74182) in 90nm FPGA, 65nm FPGA, FPGA. ...
To evaluate the effectiveness of the power gating techniques, the simulation has been performed using BPTM 45nm technology at room temperature with supply voltage of 0.7V. ...
Performance Analysis of 74182 Benchmark Circuit The performance analysis of LUT of benchmark circuit 74182 on Spartan-3A DSP, 90nm FPGA, Virtex-5, 65nm FPGA, Virtex-LP, 40nm FPGA, Kintex-7, 28nm FPGA device ...
doi:10.9790/4200-0144757
fatcat:hppxpjciqnatpcauvrtx6ppqgi
Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems
2014
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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But nowadays research extensively focuses on power too. Hence this paper demonstrates so me of the most utilized and efficient techniques for Power optimizat ion and reduction in FPGAs currently. ...
Field Programmab le Gate Arrays (FPGAs) are widely used for imp lementation of dig ital system design due to their flexibility, low time-to-market, growing density and speed. ...
Previous works have shown that the 4-input LUT is the most optimu m size as far as logic density, and utilization of resources are concerned, and this has been widely used. ...
doi:10.1109/tvlsi.2013.2290083
fatcat:j2wsmzogunazpbwdx3wicplemu
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach
2011
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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In this paper, we show that an integrated circuit-architecture-software co-design approach can be extremely effective to simultaneously improve the power and performance of a reconfigurable hardware framework ...
However, their intrinsic flexibility comes at the cost of significantly worse performance and power dissipation than their custom counterparts. ...
The primary reason behind such a penalty is the elaborate PI architecture which accounts for about 80% of power, 60% of delay, and 75% of area in deep submicron processes [3] . ...
doi:10.1109/jetcas.2011.2165232
fatcat:tlnx3mng3remfghm4fgulfd27u
FPGA Architecture: Survey and Challenges
2007
Foundations and Trends® in Electronic Design Automation
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FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. ...
There are a number of programming technologies and their differences have a significant effect on programmable logic architecture. ...
This survey has explored many issues in the complex and rapidly evolving world of pre-fabricated FPGA architectures. ...
doi:10.1561/1000000005
fatcat:ebex55milfgczim2i4wi2apbqy
PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations
2013
IEEE transactions on computers
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Speed and function density of FPGAs are increasing as transistor sizes shrink to the nanoscale. ...
performance. ...
The authors would like to thank Gold Standard Simulations Ltd and ngenics Ltd for the use of RandomSpice and MOTIVATED. ...
doi:10.1109/tc.2013.59
fatcat:df2nxtq4wvblxdhq3ool4yhyhy
Resistive computation
2010
Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10
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By implementing much of the on-chip storage and combinational logic using leakageresistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation ...
of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based ...
The authors would like to thank Yanwei Song, Ravi Patel, Sheng Li, and Todd Austin for useful feedback. ...
doi:10.1145/1815961.1816012
dblp:conf/isca/GuoIS10
fatcat:x25nvdcmjvfoth77qzaw65hpvq
Resistive computation
2010
SIGARCH Computer Architecture News
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By implementing much of the on-chip storage and combinational logic using leakageresistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation ...
of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based ...
The authors would like to thank Yanwei Song, Ravi Patel, Sheng Li, and Todd Austin for useful feedback. ...
doi:10.1145/1816038.1816012
fatcat:mywg5wkalfcdvp73cnaaolhxbe
Power Optimization of Configurable Logic Block in FPGA via Controlling Logic State of Virtual Ground Voltage
2016
International Journal of Image Graphics and Signal Processing
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Finally the result shows that reduction being at logic state of Virtual Ground Voltage =0 in a constant time period has linear effect on decreasing average power. ...
Initially different Configurable Logic Block are designed through the logic gates and then expanded via adding Look Up Table circuit (LUT) in inputs; afterwards, the samples of Configurable Logic blocks ...
ACKNOWLEDGMENT The authors wish to thank Dr. Hadi Jahanirad for his technical support. ...
doi:10.5815/ijigsp.2016.02.06
fatcat:iw2npbnazzbifba3lju67rumpi
Recent Trends and Improvisations in FPGA
2017
IOSR Journal of Electrical and Electronics Engineering
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The size of FPGAs is evolutionally breaking down by fuelling reprogrammable from 45nm to 8nm. ...
With the improvements of VLSI design in FPGA, the application areas got wider. The FPGAs architectural developments afford FPGA developers to produce effective devices day-by-day. ...
Recently, FPGAs supports vertical migration and density migration. In this paper we see some recent developments using FPGA platforms and applications. ...
doi:10.9790/1676-1203027177
fatcat:isael7icofgcxosiszjm5k6dv4
FPGA routing architecture
1999
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99
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In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transistor and tri-state buffer ...
While most commercial FPGAs contain many length 1 wires (wires that span only one logic block) we find that wires this short lead to FPGAs that are inferior in terms of both delay and routing area. ...
Acknowledgments The authors are indebted to Jordan Swartz, who modified the FPGA "architecture generator" within VPR to allow targeting of the 4000X-like architecture. ...
doi:10.1145/296399.296428
dblp:conf/fpga/BetzR99
fatcat:digjjh2mpvhhtlcu3xfrduyefu
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