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The design of a low energy FPGA

Varghese George, Hui Zhang, Jan Rabaey
1999 Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED '99  
This work presents the design of an energy efllcient FPGA architecture.  ...  The energy of the interconnect is also reduced by employing low-swing circuit techniques. These techniques have been employed to design and fabricate an FPGA.  ...  CONCLUSION The prototype of a Low Energy FPGA suitable for embedded and portable applications has been designed and implemented.  ... 
doi:10.1145/313817.313920 dblp:conf/islped/GeorgeZR99 fatcat:noe7ydhzmnfhxhfepp42pidsie

The design of a low energy FPGA

V. George, Hui Zhang, J. Rabaey
Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)  
This work presents the design of an energy efllcient FPGA architecture.  ...  The energy of the interconnect is also reduced by employing low-swing circuit techniques. These techniques have been employed to design and fabricate an FPGA.  ...  CONCLUSION The prototype of a Low Energy FPGA suitable for embedded and portable applications has been designed and implemented.  ... 
doi:10.1109/lpe.1999.799437 fatcat:vsfh6on2hfhwrcttlcpx37vtai

Design of Mobile DDR IO Standards Based Portable Devnagari Unicode Reader on FPGA
English

Tanesh Kumar, Teerath Das, Rajendra Aaseri
2016 Gyancity Journal of Engineering and Technology  
Four different 28nm 7 Series FPGA and Xilinx ISE 14.6 were taken to verify the energy efficiency and thermal efficiency of a portable Unicode reader using MOBILE DDR input/output standard.  ...  This paper aims to fill this research gap and design a portable DUR as well as make it thermal and energy efficient.  ...  Future Scope By using Mobile DDR IO Standard, we can also design both energy efficient and thermal efficient FIR Guassian low Pass Filter, Image ALU, Memory Interface, ALU, Fibonacci Generator, Frame Buffer  ... 
doi:10.21058/gjet.2016.2101 fatcat:vbuni7vucrf6tdkzvzar4ojwne

Cycle-Accurate Energy Measurement and Characterization of FPGAs

Hyung Gyu Lee, Kyungsoo Lee, Yongseok Choi, Naehyuck Chang
2005 Analog Integrated Circuits and Signal Processing  
In this paper, we introduce an in-house cycle-accurate FPGA energy measurement tool and energy characterization schemes spanning low-level to high-level design.  ...  This tool offers all the capabilities necessary to investigate the energy consumption of FPGAs for operationbased energy characterization, which is applicable to high-level and system-wide energy estimation  ...  In the second, the designer modifies the high-level architectural design of the FPGA.  ... 
doi:10.1007/s10470-005-6758-5 fatcat:e5dvltgscvgyfjseco2amphsxq

Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA).  ...  The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA.  ...  Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA Keshav Kumar, BishwajeetPandey, Amit Kant Pandit,Yousef A. Baker El-Ebiary, Salameh A.  ... 
doi:10.35940/ijitee.l1006.10812s219 fatcat:342yqsiwvjfbjk3hhc2ogd53hq

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays [chapter]

Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
2004 Lecture Notes in Computer Science  
), and a 0.18µm CMOS low-cost FPGA (Xilinx XC2S200).  ...  This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera Stratix EP1S40  ...  The results of this study are important for four reasons. First, they provide guidance to a system designer designing FPGA circuits for a low-power application.  ... 
doi:10.1007/978-3-540-30117-2_73 fatcat:m67dyai3cnbffnu5wkqutchtci

Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures

Kostas Siozios, Dimitrios Soudris
2006 2006 International Conference on Field Programmable Logic and Applications  
The novel methodology for designing a high-performance and low-energy FPGA interconnection architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced.  ...  Depending on the localized performance and energy consumption requirements of each specific region of FPGA architecture, we derive a set of corresponding spatial routing information of the applications  ...  In this paper, we propose a novel methodology for designing a high-performance and low-energy interconnection structure of an island style-based FPGA platform.  ... 
doi:10.1109/fpl.2006.311321 dblp:conf/fpl/SioziosS06 fatcat:wo7bpc2mjbhrvhocn5h5ropgd4

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Julien Lamoureux, Wayne Luk
2008 2008 NASA/ESA Conference on Adaptive Hardware and Systems  
Finally, it proposes future work that would enable the use of FPGA technology in applications where power and energy consumption is critical, such as mobile devices.  ...  This paper provides an overview of low-power techniques for field-programmable gate arrays (FPGAs ).  ...  A number of studies have investigated low-power FPGA architecture design.  ... 
doi:10.1109/ahs.2008.71 dblp:conf/ahs/LamoureuxL08 fatcat:xdtvjfckenduxosf5tpoj3v4kq

HALF: Holistic Auto Machine Learning for FPGAs [article]

Jonas Ney, Dominik Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger, Norbert Wehn
2021 arXiv   pre-print
We demonstrate the performance of HALF on a medical use case for arrhythmia detection for three different design goals, i.e. low-energy, low-power and high-throughput respectively.  ...  To efficiently implement DNNs on a specific FPGA platform for a given cost criterion, e.g. energy efficiency, an enormous amount of design parameters has to be considered from the topology down to the  ...  produces low-energy, low-power or high-throughput FPGA solutions. • A library of parameterizable low-power, ultra-low-latency hardware architectures of DNN layers. • We demonstrate FPGA implementations  ... 
arXiv:2106.14771v1 fatcat:76ahgbifd5antgtrzk6kvgq6gi

Capacitance scaling based Thermal Aware Design of Waveform Generator on Virtex-6

Sujeet Kumar Pandey, Vivek Kumar Shrivastav
2018 Gyancity Journal of Engineering and Technology  
This is an apporach to design of waveform generator on Virtex-6 FPGA that consume low amount of power. we have worked on different value of using capacitance scaling based thermal aware design waveform  ...  There is a reduction of 69.10%, 96.77%, 99.56%, and 99.82% in IOs power as the capacitance is scale down from 50000pF to 5000pF, 500pF, 50pF and 5pF respectively.  ...  Some of the researcher has done work on Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA [2] .  ... 
doi:10.21058/gjet.2018.41001 fatcat:ldnlqbqojbhbpkr44x6t5j3lh4

Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

Jingzhao Ou
2006 EURASIP Journal on Embedded Systems  
We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application  ...  In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs.  ...  ACKNOWLEDGMENTS This work is supported by the United States National Science Foundation (NSF) under Award No. CCR-0311823. The authors would like to thank Brent Milne, Haibing Ma, Shay P.  ... 
doi:10.1155/es/2006/98045 fatcat:pwiq3be6enflzkizgngbqxmh3i

Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

Jingzhao Ou, ViktorK Prasanna
2006 EURASIP Journal on Embedded Systems  
We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application  ...  In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs.  ...  ACKNOWLEDGMENTS This work is supported by the United States National Science Foundation (NSF) under Award No. CCR-0311823. The authors would like to thank Brent Milne, Haibing Ma, Shay P.  ... 
doi:10.1186/1687-3963-2006-098045 fatcat:c6b3kvcvvzgmhaoe6mqdmvgdbu

Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA

Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar
2010 2010 International Conference on Field Programmable Logic and Applications  
In this paper, we present the CNEMS design, its electrical properties and a hybrid FPGA with CNEM switches.  ...  Static power consumption has become a major concern in the design.  ...  With the nature of results obtained when compared with CMOS, it can be affirmed that CNEMS has a tremendous impact in designing energy efficient FPGA.  ... 
doi:10.1109/fpl.2010.79 dblp:conf/fpl/SirigirASKT10 fatcat:zgwuvp47srheho5a7ixqxvvcj4

Aging-based leakage energy reduction in FPGAs

Sheng Wei, Jason Xin Zheng, Miodrag Potkonjak
2013 2013 23rd International Conference on Field programmable Logic and Applications  
We synthesize the low energy design on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.  ...  The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs.  ...  INTRODUCTION As the rapid growth of FPGA applications in various domains, especially in portable digital applications and remote sensing, energy efficient FPGA designs have drawn a great deal of attention  ... 
doi:10.1109/fpl.2013.6645562 dblp:conf/fpl/WeiZP13 fatcat:7wjzrnd4tzce5laqffbeqgu3wq

Energy-efficient signal processing using FPGAs

Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-Wook Jang
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
Our designs showed a factor of 10 improvement over the embedded processor.  ...  Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II  ...  ACKNOWLEDGEMENTS The authors wish to thank Jingzhao Ou and Gokul Govindu for their contributions to the low-level simulation results.  ... 
doi:10.1145/611847.611850 fatcat:ceum6jibnbbwtkzptihe23qxi4
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