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The design and implementation of typed scheme

Sam Tobin-Hochstadt, Matthias Felleisen
2008 SIGPLAN notices  
The implementation of Typed Scheme additionally borrows elements from a range of approaches, including recursive types, true unions and subtyping, plus polymorphism combined with a modicum of local inference  ...  A Typed Scheme program can use these refinement types to keep track of arbitrary classes of values via the type system.  ...  Acknowledgements We thank Ryan Culpepper for invaluable assistance with the implementation of Typed Scheme, Matthew Flatt for implementation advice, Ivan Gazeau for his porting of existing PLT Scheme code  ... 
doi:10.1145/1328897.1328486 fatcat:g6mwd2ercveoxordpumn2rjjk4

The design and implementation of typed scheme

Sam Tobin-Hochstadt, Matthias Felleisen
2008 Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '08  
The implementation of Typed Scheme additionally borrows elements from a range of approaches, including recursive types, true unions and subtyping, plus polymorphism combined with a modicum of local inference  ...  Initial experiments with the implementation suggest that Typed Scheme naturally accommodates the programming style of the underlying scripting language, at least for the first few thousand lines of ported  ...  Acknowledgments We thank Ryan Culpepper for invaluable assistance with the implementation of Typed Scheme, Matthew Flatt for implementation advice, Ivan Gazeau for his porting of existing PLT Scheme code  ... 
doi:10.1145/1328438.1328486 dblp:conf/popl/Tobin-HochstadtF08 fatcat:2kdlafyhmnf27m5m74yuibay4a

The Design and Implementation of Typed Scheme: From Scripts to Programs [article]

Sam Tobin-Hochstadt, Matthias Felleisen
2011 arXiv   pre-print
The implementation of Typed Scheme additionally borrows elements from a range of approaches, including recursive types, true unions and subtyping, plus polymorphism combined with a modicum of local inference  ...  A Typed Scheme program can use these refinement types to keep track of arbitrary classes of values via the type system.  ...  Acknowledgements We thank Ryan Culpepper for invaluable assistance with the implementation of Typed Scheme, Matthew Flatt for implementation advice, Ivan Gazeau for his porting of existing PLT Scheme code  ... 
arXiv:1106.2575v1 fatcat:b5lt75ruerfpfdyjbpsxebevoy

THE EFFECTIVENESS OF IDEA CAPTURE SCHEMES

DESMOND J. LEACH, CHRISTOPHER B. STRIDE, STEPHEN J. WOOD
2006 International Journal of Innovation Management  
The extent of planning, publicity, feedback and management support given to the scheme, 17 and the type of rewards offered to employees, also independently account for variation in effectiveness.  ...  Publicity and non-monetary rewards, though, are found to be most decisive, 19 regardless of scheme type.  ...  In addition we tested to see if scheme type affected the strength of the effect of the 31 design features on effectiveness and found that, with one exception, it did not vary by the type of scheme.  ... 
doi:10.1142/s1363919606001521 fatcat:vcwcrc73pjfzvduq3kibvqzjla

A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique

Dhriti Duggal
2013 International Journal of Electrical and Computer Engineering (IJECE)  
The proposed scheme demonstrates an overall reduction of 76.68% in crosstalk delay and 56.33% in chip area and transistor count. 79.58% power reduction is achieved in full-custom design implementation  ...  However, our proposed codec scheme focuses on all types of couplings i.e.  ...  Final output of the implemented codec scheme is shown in Figure 6 . Table 2 shows the total power consumption by the implemented codec scheme as per the semi-custom design approach.  ... 
doi:10.11591/ijece.v3i4.3173 fatcat:qnrtbbdncrhclhhdmo5oeycjca

CMOS Control Enabled Single-Type FET NASIC

Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design.  ...  This is enabled by CMOS providing control signals that coordinate the operation of the logic implemented in the nanoscale.  ...  Fig. 1 illustrates the design of a 1-bit NASIC full adder in a dynamic style with two types of FETs required for AND-OR logic implementation.  ... 
doi:10.1109/isvlsi.2008.92 dblp:conf/isvlsi/NarayananLWM08 fatcat:vve2juhaajfzhl6mycrm2oisfy

Design and Implementation of Software Objects in Hardware

Fu-Chiung Cheng, Hung-Chi Wu
2006 Computer Design (ICCD '99), IEEE International Conference on  
The result of experiments shows that object-reference scheme is much better than the other 3 schemes in terms of hardware cost, energy consumption and speed for FPGA implementation.  ...  Data-Memory mapping schemes are investigated and four hardware object design schemes are proposed and implemented on a CAD tool.  ...  Fig 1 1 HO implementation of CLOL mapping and CICO scheme Fig 2 2 Efficient HO implementation and Object-reference scheme Fig 3 3 Design flow of method circuit implementation (b).  ... 
doi:10.1109/iccd.2006.4380856 dblp:conf/iccd/ChengW06 fatcat:v3owpxvvybaahcvejfvx2xfalu

Implementation of Data Encoding Schemes for Power Reduction in Network on Chip Links

2018 International Journal of Recent Trends in Engineering and Research  
This effort investing sates the reduction of transition activity using gray coding schemes. Our advanced scheme does not require any change of the routers and link architecture.  ...  An investigational result has shown the effectiveness of the proposed schemes, with respect of power dissipation and area overhead in the Network Interface (NI) as compared with data encoding.  ...  The advances in fabrication technology allow designers to implement a whole system on a single chip, but the inherent design complexity of such systems makes it hard to fully explore the technology potential  ... 
doi:10.23883/ijrter.conf.20171216.013.8u1ld fatcat:bxqitidl25dgjht5i4zr5mwmaq

Homomorphic Data Isolation for Hardware Trojan Protection [article]

M. Tarek Ibn Ziad, Amr Alanwar, Yousra Alkabani, M. Watheq El-Kharashi, Hassan Bedour
2015 arXiv   pre-print
We implement two partial homomorphic designs based on ElGamal encryption/decryption scheme. The first design is a multiplicative homomorphic, whereas the second one is an additive homomorphic.  ...  We implement the proposed designs on a low-cost Xilinx Spartan-6 FPGA. Area utilization, delay, and power consumption are reported for both designs.  ...  Implementation: Fig. 3 shows the block diagram for our implementation of the CEG encryption/decryption scheme.  ... 
arXiv:1505.05226v2 fatcat:3npzh2kgvrg77ctfwu3x5us2ci

Economic information from Smart Meter: Nexus Between Demand Profile and Electricity Retail Price Between Demand Profile and Electricity Retail Price [article]

Yang Yu, Guangyi Liu, Wendong Zhu, Fei Wang, Bin Shu, Kai Zhang, Ram Rajagopal, Nicolas Astier
2016 arXiv   pre-print
We develop a criteria system to evaluate the economic efficiency of an implemented retail price scheme in a distribution system by comparing profile clustering and daily-average clustering.  ...  Our criteria system can examine the extent of a retail price scheme's inefficiency even without information about the distribution system's daily cost structure.  ...  When consumer's MCI is injective function of their demand profile, we define the "the degree of consistency between the implemented price scheme and an economically optimal price design" as the difference  ... 
arXiv:1701.02646v1 fatcat:o37lsvvooveyzaxog2eijllisq

An optimized MC interpolation architecture for HEVC

Zhengyan Guo, Dajiang Zhou, Satoshi Goto
2012 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
For this component, we propose an efficient VLSI design which is composed of a reconfigurable filter, an optimized pipeline engine organization, and a filter reuse scheme.  ...  This results in 30% area saving from a non-optimized design. The proposed implementation supports a maximal throughput of QFHD@60fps.  ...  Filter Reuse Scheme Parallelized design is implemented to improve the throughput of this subsystem. We call it dual-engine structure.  ... 
doi:10.1109/icassp.2012.6288083 dblp:conf/icassp/GuoZG12 fatcat:eklqe7ietjcblb47w5qxbr4qoq

How are pay-for-performance schemes in healthcare designed in low- and middle-income countries? Typology and systematic literature review

Roxanne J. Kovacs, Timothy Powell-Jackson, Søren R. Kristensen, Neha Singh, Josephine Borghi
2020 BMC Health Services Research  
We find that there is substantial heterogeneity in the design of P4P schemes in LMICs and pinpoint precisely how scheme design varies across settings.  ...  Pay for performance (P4P) schemes provide financial incentives to health workers or facilities based on the achievement of pre-specified performance targets and have been widely implemented in health systems  ...  Implementation, funding and complementary reforms Some differences in scheme design appear to be influenced by the organisation funding and implementing the scheme.  ... 
doi:10.1186/s12913-020-05075-y pmid:32264888 fatcat:5jo5aa3bv5blhpkqaascbu4jle

Low power analysis of DLX processor datapath using a novel clocking scheme

R. K. Megalingam, S. Hassan, T. Rao, A. Mohan, V. Perieye
2010 Proceedings of the International Conference and Workshop on Emerging Trends in Technology - ICWET '10  
We have mainly focused on implementing the pipelined DLX processor datapath in HDL using two different clocking schemes as in [1] and analyzed the power consumption.  ...  Low power VLSI circuit design is a core area for current research activities. Power reduction without compromising the performance is the vital concern for processor design.  ...  We gratefully acknowledge the Almighty GOD who gave us strength and health to successfully complete this venture.  ... 
doi:10.1145/1741906.1742107 dblp:conf/icwet/MegalingamHRMP10 fatcat:hygiw7lyhnfctkymjciulglipe

Design and Chip Implementation of A SMI/MVDR Dual-mode Beamformer for Wireless MIMO Communication Systems

Kuan-Ting Chen, Yin-Tsung Hwang, Cheng-Yi Huang
2020 IEEE Access  
In chip implementation, a TSMC 90nm UTM process technology is used and the design specs largely follow the requirements of IEEE 802.11ac standard. The core size of the chip design is 0.68mm 2 .  ...  It can complete the computation of a new beamforming vector (of size 8) every 0.64us and exhibits the highest throughput among the 6 compared designs.  ...  These include identifying the shared modules of two beamforming modes, approximating the Hermitian type auto-correlation matrix with a Toeplitz type counterpart, and developing an efficient computing scheme  ... 
doi:10.1109/access.2020.2986028 fatcat:ezanpqetfjbs5jrdm3ylytjgqe

Bee: an integrated development environment for the Scheme programming language

MANUEL SERRANO
2000 Journal of functional programming  
This article details the facilities of the Bee, its user interface, and presents an overview of the implementation of its main components.  ...  The paper describes how to implement these tools for Scheme with a small development team by reusing analgous tools developed for C.  ...  Acknowledgements Many thanks to Barrie Stott, Bahman Rafatjoo, Céline and the anonymous referees of the Journal of Functional Programming for their helpful feedbacks on this work.  ... 
doi:10.1017/s0956796800003725 fatcat:5w5rdmxphrbbjfojvsdfv7c66q
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