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The bell is ringing in speed-scaled multiprocessor scheduling

Gero Greiner, Tim Nonner, Alexander Souza
2009 Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures - SPAA '09  
migration, where B α is the αth Bell number, that is, the number of partitions of a set of size α.  ...  This paper investigates the problem of scheduling jobs on multiple speedscaled processors without migration, i.e., we have constant α > 1 such that running a processor at speed s results in energy consumption  ...  [14] to obtain a constant competitive online algorithm for non-speed-scaled multiprocessor scheduling with weighted flow time and speed augmentation.  ... 
doi:10.1145/1583991.1583996 dblp:conf/spaa/GreinerNS09 fatcat:pir2gj426jgj5gdk3c2gghlygm

The Bell Is Ringing in Speed-Scaled Multiprocessor Scheduling

Gero Greiner, Tim Nonner, Alexander Souza
2013 Theory of Computing Systems  
migration, where B α is the αth Bell number, that is, the number of partitions of a set of size α.  ...  This paper investigates the problem of scheduling jobs on multiple speedscaled processors without migration, i.e., we have constant α > 1 such that running a processor at speed s results in energy consumption  ...  [14] to obtain a constant competitive online algorithm for non-speed-scaled multiprocessor scheduling with weighted flow time and speed augmentation.  ... 
doi:10.1007/s00224-013-9477-9 fatcat:k3dy6hddlvel5g75kudfclu5om

Scalable, parallel computers: Alternatives, issues, and challenges

Gordon Bell
1994 International journal of parallel programming  
Program or problem scalability, first observed by Gustafson et is a property of a program/machine combination that determines the ability of a problem to operate at various scales (sizes) on a given scale  ...  However, it has been the experience of the scientists in our research group that a certain amount of long-distance communication is unavoidable for these types of applications.  ...  In the future, the bus could be replaced by a ring, providing the essential features of a bus, but scales automatically with generation, i.e. clock speed since each processor only drives a neighbor.  ... 
doi:10.1007/bf02577791 fatcat:jnvgpsftabcnnabkmpcm5kifqq

LSI and minicomputer system architecture

L. Seligman
1971 Proceedings of the November 16-18, 1971, fall joint computer conference on - AFIPS '71 (Fall)  
The organization of the control programs for the multiprocessor complex is almost identical to the organization used in the (essentially) single processor telephone exchange control developed at Bell Laboratories  ...  The major difference between the two approaches is that a spatial distribution of programs across several processors is used in the former, while a time division of the processor is used in the Bell System  ... 
doi:10.1145/1478873.1478972 dblp:conf/afips/Seligman72 fatcat:6zp2pspsrresre3nqw2alopdoq

Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors [chapter]

Nabil Hasasneh, Ian Bell, Chris Jesshope
2006 Lecture Notes in Computer Science  
It is shown that this arbiter can be extended easily to support large numbers of processors and can be used for chip multiprocessor arbitration purposes.  ...  This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL.  ...  the position in the ring and in sequence order.  ... 
doi:10.1007/11682127_18 fatcat:4oy6xtikxra6dee2n5zxocjxvq

Cloud controlled intrusion detection and burglary prevention stratagems in home automation systems

A. Maiti, S. Sivanesan
2012 2012 2nd Baltic Congress on Future Internet Communications  
Thresholding algorithm along with OpenCV is used to split an image into smaller segments, or junks, using at least one color or gray scale value to define their boundary.  ...  As soon as an intrusion is detected, an SMS alert is given to the user and the user can view the video of the intruded room and secure his house by giving an alert to the neighborhood.  ...  The User's IP Address is 10.0.0.17.The User views the video of the intruded room and if it's a valid intrusion, an alarm bell rings to caution the neighbors' and a message is sent to the neighbor's and  ... 
doi:10.1109/bcfic.2012.6218000 dblp:conf/bcfic/MaitiS12 fatcat:pmdv2vap7ffozlywjko3etyhuy

3. A Bibliography on Parallel and Vector Numerical Algorithms [chapter]

James M. Ortega, Robert G. Voigt, Charles H. Romine
1990 Parallel Algorithms for Matrix Computations  
Vectorization of a penalty function algorithm for well scheduling, in Gary [3] I. ABU-SHOMAYS [1985].  ...  Since parallel and vector computation is expanding rapidly, we hope that the references we have collected over the years will be of some value to researchers entering the field.  ...  BELL [1985]. Multis: A new class of multiprocessor computers, Science, 228, pp. 462-467. [130] J. BELL A N D G . PATTERSON [1987]. Data organization in large numerical computations, J .  ... 
doi:10.1137/1.9781611971705.ch3 fatcat:pkjwqy26bfcjneyf76jqebybei

Technologies and building blocks for fast packet forwarding

W. Bux, W.E. Denzel, T. Engbersen, A. Herkersdorf, R.P. Luijten
2001 IEEE Communications Magazine  
The industry's response to the need for wirespeed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special  ...  We provide a review of the state of the art and the future of packet processing and switching.  ...  Special thanks go to Jan van Lunteren for his valuable input to the discussion of table lookup and classification issues.  ... 
doi:10.1109/35.894379 fatcat:sailcyxj2ffhznvmbaguiflvri

Supporting Microthread Scheduling and Synchronisation in CMPs

Ian Bell, Nabil Hasasneh, Chris Jesshope
2006 International journal of parallel programming  
Scalable implementations of such support structures are given and the feasibility of large-scale CMPs is investigated by giving detailed area estimate of these structures.  ...  Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems.  ...  project, which has been funded in their GLANCE program, project number: 600.643.000.05N07.  ... 
doi:10.1007/s10766-006-0017-y fatcat:w7l3s4r6mnevpjzpuv5lhmebfm

Algorithms for Integrated Routing and Scheduling for Aggregating Data from Distributed Resources on a Lambda Grid

A. Banerjee, Wu-chun Feng, D. Ghosal, B. Mukherjee
2008 IEEE Transactions on Parallel and Distributed Systems  
The challenge is 1) to identify routes (that is, circuits) in the lambda-grid network, along which files should be transmitted, and 2) to schedule the transfers of these files over their respective circuits  ...  This helps in reducing the total time to transfer all the files, which is an important metric.  ...  ACKNOWLEDGMENTS The authors gratefully acknowledge Jeremy Archuleta, formerly of Los Alamos National Laboratory and now at Virginia Tech, for his help in setting up the networking infrastructure for their  ... 
doi:10.1109/tpds.2007.1112 fatcat:qygbazidczcdhk2jbmrnxb7n3q

Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers

David E. Taylor, Jonathan S. Turner, John W. Lockwood, Edson L. Horta
2002 Computer Networks  
The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware.  ...  This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers.  ...  Acknowledgements The authors would like to thank David Parlour and Xilinx, Inc. for their support and efforts to aid in this research.  ... 
doi:10.1016/s1389-1286(01)00289-4 fatcat:fqvst23iyjagvpnwjagglmuug4

A case for intelligent RAM

D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, K. Yelick
1997 IEEE Micro  
Merging processing and memory into a single DRAM chip could revolutionize the semiconductor industry.  ...  same speed as those in the Alpha.  ...  ., where he cooperated with the Digital Video Group at Bell Communications Research (Bellcore). Kimberly Keeton is a PhD candidate in computer science at UC Berkeley.  ... 
doi:10.1109/40.592312 fatcat:fkjx3bx5k5b7dhifh54c5vrmgu

Introduction to parallel computing

1992 ChoiceReviews  
A basic understanding of the parallel computing techniques that assist in the capture and utilization of that computational power is essential to appreciate the capabilities and the limitations of parallel  ...  In addition, an understanding of technical vocabulary is critical in order to converse about parallel computers.  ...  The phone rings (and the caller is blocked) until the recipient answers the phone. It is possible that the recipient is sitting by his phone waiting for it to ring.  ... 
doi:10.5860/choice.30-1558 fatcat:7qgaeun2ujgcjj3cc3bfbvvbi4

Introduction to parallel computing

2004 ChoiceReviews  
A basic understanding of the parallel computing techniques that assist in the capture and utilization of that computational power is essential to appreciate the capabilities and the limitations of parallel  ...  In addition, an understanding of technical vocabulary is critical in order to converse about parallel computers.  ...  The phone rings (and the caller is blocked) until the recipient answers the phone. It is possible that the recipient is sitting by his phone waiting for it to ring.  ... 
doi:10.5860/choice.42-0990 fatcat:kiymwofenbavfdixftjhnuavx4

Evaluating and designing software mutual exclusion algorithms on shared-memory multiprocessors

X. Zhang, Y. Yan, R. Castaneda
1996 IEEE Parallel & Distributed Technology Systems & Applications  
Examples of interconnection networks for large-scale shared-memory multiprocessors are the multistage interconnection network (BBN Butterfly systems), hierarchical ring structure (KSR systems), cluster-based  ...  First, program-thread scheduling and execution should efficiently exploit hierarchical locality by processing referenced data in a local cache or in caches in the local ring as much as possible.  ... 
doi:10.1109/88.481663 fatcat:rdpg2oxmofas5cdeu5btuzhox4
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