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Computational Optimization of Placement and Routing using Genetic Algorithm

S. Nazeer Hussain, K. Hari Kishore
2016 Indian Journal of Science and Technology  
In the VLSI chip designing process, Floor-planning is one of the vital stages which in turn have Placement and Routing tasks.  ...  The searching for best solutions is carried out by Genetic Algorithm (GA) on each iteration since these algorithms is already known and proven to solve similar type of problems.  ...  VLSI Design engineer can able to reconfigure it for various digital applications based on computer aided design flow. There is various design steps involved in the process.  ... 
doi:10.17485/ijst/2015/v8i1/104400 fatcat:5lpkdeu6jfem7daee6exrjw44q

A genetic algorithm approach for global routing of VLSI circuits

D Ravikumar, Arun Raaza, V Devi, E Gopinathan
2018 International Journal of Engineering & Technology  
The last ten years have been witnessing the feature of swelling success of Genetic Algorithms in their application to VLSI physical design.  ...  Very Large Scale Integrating (VLSI) design has the objectives of producing the layout for integrating circuits.  ...  Physical design is known to be a significant step in the creation of a VLSI circuit. Logical representation of the system under design forms the input to the physical design.  ... 
doi:10.14419/ijet.v7i2.21.12450 fatcat:ajax4ewsbngbxjdp4nclmnzgmm

Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research

Nasreddine Hireche, J.M. Langlois, Gabriela Nicolescu
2006 2006 Canadian Conference on Electrical and Computer Engineering  
In this article we provide a state of the art review for this field of research. We identify specific algorithmic problems and how hardware architectures can be designed to solve them.  ...  Comparison of DNA sequences and genes can be useful to investigate the common functionalities of the corresponding organisms and to get a better understanding of how specific genes or groups of genes are  ...  The authors presented the design of a database scanning application based on the SW algorithm in order to derive efficient mappings onto these architectures.  ... 
doi:10.1109/ccece.2006.277302 dblp:conf/ccece/HirecheLN06 fatcat:wima5c3acjctnpviolb7exrmhu

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis

R. Karri, B. Iyer, I. Koren
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Phantom redundancy uses extra interconnect to make the resulting data path reconfigurable in the presence of any (single) functional unit failure.  ...  We developed a genetic algorithm based register transfer level synthesis approach to incorporate phantom redundancy constraints.  ...  In many VLSI applications, it is not uncommon to experience circuit yields on the order of 10% or even less thereby increasing the cost of manufacturing the circuit.  ... 
doi:10.1109/tcad.2002.800450 fatcat:cx4737dt5nh6nhgcxx7lv4cgyq

A Metaheuristic Algorithm for VLSI Floorplanning Problem

2019 International journal of recent technology and engineering  
Floorplanning plays an important role within the physical design method of very large Scale Integrated (VLSI) chips.  ...  It's a necessary design step to estimate the chip area before the optimized placement of digital blocks and their interconnections.  ...  Genetic algorithms combined with Harmony search algorithm are extensively employed in entirely dissimilar forms to resolve many more VLSI floorplanning issues.  ... 
doi:10.35940/ijrte.b1052.0782s519 fatcat:d4qb44jds5c3bdvwgattvi4veq

A Genetic Algorithm for VLSI Floorplanning [chapter]

Christine L. Valenzuela, Pearl Y. Wang
2000 Lecture Notes in Computer Science  
The classical floor planning techniques use block packing to minimize chip area, by making use of algorithms like B-TREE representation, simulated annealing.  ...  To get an optimal solution it is imperative to choose an efficient, cost effective algorithm. This paper presents a genetic algorithm to provide a solution to the floor planning technique.  ...  [5] This is particularly advantageous to real-time applications such as reconfiguration of evolvable hardware.  ... 
doi:10.1007/3-540-45356-3_66 fatcat:e5i4n3urczgwzoojxozcw26s5a

Table of contents

2004 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat No 04CH37512) ISCAS-04  
............II -517 APPLICATION Wing-Kin Chan, Chiu-Sing Choy, Cheong-Fat Chan, Kong-Pang Pun, The Chinese University of Hong Kong, Hong Kong SAR of China VLSI-L15: INTERCONNECT VLSI-L15.1: DECOUPLING  ...  Willingham, Izzet Kale, University of Westminster, United Kingdom VLSI-L2: VIDEO VLSI-L2.1: A DISTRIBUTED TS-MUX ARCHITECTURE FOR MULTI-CHIP EXTENSION ................................II -261 BEYOND THE  ... 
doi:10.1109/iscas.2004.1328114 fatcat:xmvsmkhxgbb55ftuygqomthikm

Bio-Inspired Microsystem for Robust Genetic Assay Recognition

Jaw-Chyng Lue, Wai-Chi Fang
2007 2007 Frontiers in the Convergence of Bioscience and Information Technologies  
In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals.  ...  A posterior VLSI artificial neural network (ANN) processor chip is used for analyzing the processed signals from the differential logarithm stage.  ...  ACKNOWLEDGMENT The authors would like to thank Dr. Armand R.  ... 
doi:10.1109/fbit.2007.145 dblp:conf/fbit/LueF07 fatcat:fbuzp2heejfvvjchvucbuqcf44

Bio-Inspired Microsystem for Robust Genetic Assay Recognition

Jaw-Chyng Lue, Wai-Chi Fang
2008 Journal of Biomedicine and Biotechnology  
In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals.  ...  A posterior VLSI artificial neural network (ANN) processor chip is used for analyzing the processed signals from the differential logarithm stage.  ...  ACKNOWLEDGMENT The authors would like to thank Dr. Armand R.  ... 
doi:10.1155/2008/259174 pmid:18566679 pmcid:PMC2426746 fatcat:2bzfdwlphrfxrhgpyd2jbqhnhm

A Survey of FPGAs for Acceleration of High Performance Computing and their Application to Computational Molecular Biology

Tirath Ramdas, Greg Egan
2005 TENCON 2005 - 2005 IEEE Region 10 Conference  
Software implementation of some sequence alignment algorithms suffer quadratic time performance, however CCM implementations may be highly parallelized and consequently provide linear time performance.  ...  Molecular biocomputation workflows traditionally involve days of compute time to align DNA/protein sequences.  ...  The move to C-like HDLs would only be reasonable if this new breed of HDLs allow the production of designs that exhibit reasonably good QoR.  ... 
doi:10.1109/tencon.2005.300963 fatcat:hinufcyrpfd47p45pugdzm2bay

An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits

Dzmitry Maliuk, Haralampos-G. Stratigopoulos, Yiorgos Makris
2010 2010 IEEE 16th International On-Line Testing Symposium  
The results are compared to those of the software neural networks of equivalent topologies and limitations concerning the practical applicability are discussed.  ...  The network is trained in the chip-in-the-loop fashion with the simulated annealing-based parallel weight perturbation training algorithm.  ...  The network presented herein was designed with two key objectives in mind: reconfigurability to explore various network models for a given application and simplicity of training.  ... 
doi:10.1109/iolts.2010.5560230 dblp:conf/iolts/MaliukSM10 fatcat:36unbny3f5c6rcw5trfx47tmde

A Survey on Reconfigurable System-on-Chips

Hung Kiem Nguyen, Tu Xuan Tran
2018 REV Journal on Electronics and Communications  
Afterwards, the key issues of designing the reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips.  ...  The unique characteristic of such systems is integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip.  ...  (PSO), Evolution Algorithm (EA), Genetic Algorithm (GA), etc.  ... 
doi:10.21553/rev-jec.147 fatcat:zqjzktktbjh4los7luipp45cvy

Synthesis of low-power DSP systems using a genetic algorithm

M.S. Bright, T. Arslan
2001 IEEE Transactions on Evolutionary Computation  
The synthesis tool genetic algorithm for low-power synthesis (GALOPS) uses a genetic algorithm to apply power-reducing transformations to high-level signal-processing designs, producing designs that satisfy  ...  This paper presents a new tool for the synthesis of low-power VLSI designs, specifically, those designs targeting digital signal processing applications.  ...  The Genetic Algorithm A genetic algorithm requires a diverse initial population to start searching the solution space from multiple locations.  ... 
doi:10.1109/4235.910463 fatcat:lcqrdmdatfdcjihyu5xgd7g2mq

Configware and morphware going mainstream

Jürgen Becker, Reiner Hartenstein
2003 Journal of systems architecture  
The paper addresses a broad readership in information technology, computer science and related areas, and gives an introduction to fine grain and coarse grain morphware, reconfigurable computing, and its  ...  Doubling approximately only every 10 years the growth of memory communication bandwidth is extremely slow (Fig. 1) . Because of the von Neumann bottleneck, memory bandwidth is an important issue.  ...  Critics disfavor the trend to love genetic algorithms in other applications areas, even where simulated annealing is more efficient, like e.g. for simultaneous placement and routing which could be viewed  ... 
doi:10.1016/s1383-7621(03)00073-0 fatcat:ebvbvahp35cdfmymcru6e73yrq

Artificial neural networks in hardware: A survey of two decades of progress

Janardan Misra, Indranil Saha
2010 Neurocomputing  
We study the overall progress in the field across all major ANN models, hardware design approaches, and applications.  ...  Chip design approaches (digital, analog, hybrid, and FPGA based) at neuronal level and as neurochips realizing complete ANN models are studied.  ...  In contrast to Custom VLSI, the FPGAs are readily available at a reasonable cost and have a reduced hardware development cycle.  ... 
doi:10.1016/j.neucom.2010.03.021 fatcat:regzu6sshvekzd5wxcuaiytgqu
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