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From LOTOS to LNT [chapter]

Hubert Garavel, Frédéric Lang, Wendelin Serwe
2017 Lecture Notes in Computer Science  
We review the successive enhancements of LOTOS that led to the definition of three languages: E-LOTOS (ISO International Standard 15437:2001), then LOTOS NT, and finally LNT.  ...  protocols and distributed systems, and, on the other hand, to two proposals (Extended LOTOS and Modular LOTOS) for making LOTOS a simpler and more expressive language.  ...  Section 2 recalls the contributions of Ed Brinksma to the definition of LOTOS and gives a brief account of the impact of this language in academia and industry.  ... 
doi:10.1007/978-3-319-68270-9_1 fatcat:ulzu74ck7na75o3apfrf6r4wgi

Compiler Construction Using LOTOS NT [chapter]

Hubert Garavel, Frédéric Lang, Radu Mateescu
2002 Lecture Notes in Computer Science  
It combines the strong theoretical foundations of process algebras with language features suitable for a wide industrial use.  ...  Lotos NT is an hybrid between imperative and functional languages.  ... 
doi:10.1007/3-540-45937-5_3 fatcat:3mdvtdyk3fg67o7xcrofrcjhlq

An Eclipse-Based Editor to Support LOTOS Newcomers

Giuseppe De Ruvo, Antonella Santone
2014 2014 IEEE 23rd International WETICE Conference  
We present ELOTON, an Eclipse-based Editor to help people who want to approach the Language of Temporal Ordering Specification (LOTOS).  ...  LOTOS has been widely used for the specification of large data communication systems.  ...  To cope with the first problem, several specification languages have been developed. Some tools use process algebras as, for example, CCS [6] , LOTOS [7] , CSP [22] .  ... 
doi:10.1109/wetice.2014.39 dblp:conf/wetice/RuvoS14 fatcat:atelw46xozgcxl7upnw3gp5w3e

Graphic visualization and animation of LOTOS execution traces

Bernard Stepien, Luigi Logrippo
2002 Computer Networks  
These are made possible by enforcing specific LOTOS styles and by providing certain mappings between the elements of LOTOS actions and the elements of the graphic notation.  ...  The main application area considered is the visualization and animation of specifications of telephony systems. The use of these tools in software design is discussed briefly.  ...  The anonymous referees provided also a number of useful suggestions.  ... 
doi:10.1016/s1389-1286(02)00356-0 fatcat:tbvcsj6m3vedvehzdcem2nv37a

A common compiler for LOTOS and SDL specifications

C. Binding, W. Bouma, M. Dauphin, G. Karjoth, Y. Yang
1992 IBM Systems Journal  
The language has two components, one dealing with the algebraic de- scription of data based on the algebraic specifi- cation language ACT ONE?  ...  Encontre, “GEODE: An Industrial Environment for Designing Real Time Distributed Systems in SDL,” SDL ’89: The Language at Work, M. M. Marques and O.  ... 
doi:10.1147/sj.314.0668 fatcat:gstajhf75rgbdigb3odyceji5e

Specification and Verification of Synchronous Hardware using LOTOS [chapter]

Ji He, Kenneth J. Turner
1999 IFIP Advances in Information and Communication Technology  
This paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS).  ...  After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them.  ...  This is not so surprising since LOTOS is an expressive language.  ... 
doi:10.1007/978-0-387-35578-8_17 fatcat:vpmlrpgmxjf63fax23wexn4264

Verifying and Testing Asynchronous Circuits Using Lotos [chapter]

Ji He, Kenneth J. Turner
2000 IFIP Advances in Information and Communication Technology  
An algorithm is also presented for generating and applying implementation tests based on a specification. Tools have been developed for automated verification of conformance and generation of tests.  ...  It is shown how DILL (Digital Logic in LOTOS) can be used to specify, verify and test asynchronous hardware designs.  ...  Introduction Background DILL (Digital Logic in LOTOS, e.g. [9, 10] ) is an approach, a language and a toolset for specifying, analysing and testing digital hardware designs.  ... 
doi:10.1007/978-0-387-35533-7_17 fatcat:4jy7uxlrnngz3e2gk7ob6raw3q

Verification of an industrial SystemC/TLM model using LOTOS and CADP

Hubert Garavel, Claude Helmstetter, Olivier Ponsini, Wendelin Serwe
2009 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design  
In this paper, we present an approach to the validation of a SystemC/TLM description by translation into LOTOS, reusing as much as possible of the original SystemC/TLM C++ code.  ...  In general, formal verification of SystemC/TLM relies on the translation of the complete model into a language accepted by a verification tool.  ...  Hersemeule (STMicroelectronics) for providing us with the BDisp case study and for their help with this work.  ... 
doi:10.1109/memcod.2009.5185377 dblp:conf/memocode/GaravelHPS09 fatcat:pxt6fp2bybagtakz6uvgyzlr6a

Specifying and Verifying the SYNERGY Reconfiguration Protocol with LOTOS NT and CADP [chapter]

Fabienne Boyer, Olivier Gruber, Gwen Salaün
2011 Lecture Notes in Computer Science  
As an illustration of this trend, this paper reports on our experience with the co-design and specification of the reconfiguration protocol of a component-based platform, intended as the foundation for  ...  We wrote the specification in Lotos NT, whose evolution from the E-Lotos standard proved especially suited to this work. We extensively verified the protocol using the Cadp toolbox.  ...  The author would like to thank Frédéric Lang and the anonymous reviewers for their comments on a former version of this paper.  ... 
doi:10.1007/978-3-642-21437-0_10 fatcat:vq362yajprh7lb2vlhbsq6puae

Translating Hardware Process Algebras into Standard Process Algebras: Illustration with CHP and LOTOS [chapter]

Gwen Salaün, Wendelin Serwe
2005 Lecture Notes in Computer Science  
In a second step, we describe the translation of Chp into the standard process algebra Lotos, in order to allow the application of the Cadp verification toolbox to asynchronous hardware designs.  ...  A prototype translator from Chp to Lotos has been successfully used for the compositional verification of the control part of an asynchronous circuit implementing the DES (Data Encryption Standard ).  ...  We are grateful to Edith Beigné, François Bertrand, Dominique Borrione, Marc Renaudin, and Pascal Vivet for interesting discussions on Chp and Tast, in particular on the semantics of the probe operator  ... 
doi:10.1007/11589976_17 fatcat:v3naiwefdzdj7gl6y4daqviage

On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

Hubert Garavel, Gwen Salaün, Wendelin Serwe
2009 Science of Computer Programming  
A translator from Chp to Lotos has been implemented and successfully used for the compositional verification of two industrial case studies, namely an asynchronous implementation of the Des (Data Encryption  ...  toolbox for Lotos.  ...  We also thank the same colleagues from Cea/Leti laboratory for their cooperation in the Des and Anoc case studies.  ... 
doi:10.1016/j.scico.2008.09.011 fatcat:dfr35qxbnrbqhfwi6yayio7wwu

An experiment in using RT-LOTOS for the formal specification and verification of a distributed scheduling algorithm in a nuclear power plant monitoring system [chapter]

L. Andriantsiferana, J.-P. Courtiat, R. C. Oliveira, L. Picci
1997 Formal Description Techniques and Protocol Specification, Testing and Verification  
The paper relates an industrial experiment performed jointly by LAAS-CNRS and Electricite de France (EdF in short) for assessing the application of a formal method to the reverse engineering of (a part  ...  The formal method used for the experiment is RT-LOTOS, a temporal extension of the LOTOS standard Formal Description Technique (FDT in short) .  ...  Introduction The paper describes an experiment dealing with the formal specification and validation of a fault-tolerant monitoring system designed for the control room of French N4 nuclear power plants  ... 
doi:10.1007/978-0-387-35271-8_27 fatcat:zcibsu3hhrbblj2zgxbmkihtbq

Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular

Hubert Garavel
2008 Electronical Notes in Theoretical Computer Science  
This suggests a new generation of formal specification languages that would combine the concurrent features of process calculi with the standard concepts present in algorithmic languages.  ...  In this report we review the current state of concurrency theory with respect to its industrial impact.  ...  In this school of thinking, every language feature must be algebraical: a concurrent language is an algebra; a concurrent program is an algebraic term; the semantics of process operators is defined by  ... 
doi:10.1016/j.entcs.2008.04.009 fatcat:cj2gvg3xsvg7jbcztlbktujm6a

Introduction to the PSTV-IX

Ed Brinksma, Giuseppe Scollo, Chris A. Vissers
1991 Computer networks and ISDN systems  
All of the four papers that form the present collection were improved by acute, constructive criticism by the referees, to whom, also on behalf of the readers, we extend a hearty thanks for their outstanding  ...  Bochmann and Bj~rn Pehrson, who contributed the reports on the workshop sessions they respectively chaired.  ...  Vaandrager introduced ACP, the Algebra of Communicating Processes, as an algebraic framework for the specification and verification of concurrent, communicating processes. • G. Kahn and D.  ... 
doi:10.1016/0169-7552(91)90078-q fatcat:abmyrcfipbhprdrlrgvlcjbxwa

On Combining Functional Verification and Performance Evaluation Using CADP [chapter]

Hubert Garavel, Holger Hermanns
2002 Lecture Notes in Computer Science  
In this paper, we describe how the Cadp toolbox, originally designed for verifying the functional correctness of Lotos specifications, can also be used for performance evaluation.  ...  We illustrate the proposed approach by the performance study of the Scsi-2 bus arbitration protocol.  ...  We are grateful to Massimo Zendri for bringing the Scsi-2 example to our attention, and to Moëz Cherif (formerly at Inria/Vasy) for helping us to develop the Bcg Min tool.  ... 
doi:10.1007/3-540-45614-7_23 fatcat:o4cd2ykrizawpjnfzyz4s4gszm
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