Filters








5 Hits in 2.1 sec

The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture

D.S. Henry, B.C. Kuszmaul, V. Viswanath
1999 Proceedings 20th Anniversary Conference on Advanced Research in VLSI  
The Ultrascalar datapath is simple, has the full functionality of today's superscalars and has excellent asymptotic properties.  ...  The Ultrascalar processor when attached to a conventional memory subsystem exploits exactly the same instruction-level parallelism as that of today's superscalar processors.  ... 
doi:10.1109/arvlsi.1999.756053 dblp:conf/arvlsi/HenryKV99 fatcat:tuuefh4aojeifdv6h4abhsnmaa

A Comparison of Asymptotically Scalable Superscalar Processors

B. C. Kuszmaul, D. S. Henry, G. H. Loh
2002 Theory of Computing Systems  
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community.  ...  Ultrascalar I transmits an entire copy of the register file to each station, and the station chooses which register values it needs based on the instruction. Ultrascalar I uses an H-tree layout.  ...  Yale graduate student Vinod Viswanath laid out the Ultrascalar I datapath in VLSI.  ... 
doi:10.1007/s00224-001-1029-z fatcat:nfxub7wdlbb5hnclgj5tzgx2qm

A comparison of scalable superscalar processors

Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh
1999 Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures - SPAA '99  
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community.  ...  The Ultrascalar I uses an H-tree layout.  ...  Yale graduate student Vinod Viswanath layed out the Ultrascalar I datapath in VLSI.  ... 
doi:10.1145/305619.305633 dblp:conf/spaa/KuszmaulHL99 fatcat:yvylxfpvxjfjzhzz3lzdwxvgce

Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture

D. Morano, A. Khalafi, D. R. Kaeli, A. K. Uht
2003 SIGARCH Computer Architecture News  
However, several problems are associated with such microarchitectures, including scalability, issues related to control flow, and memory latency.  ...  We present a basic overview of our microarchitecture and discuss how it addresses scalability as we attempt to execute many instructions in parallel.  ...  The Ultrascalar machine [6] achieves asymptotic scalability, but only realizes a small amount of IPC due to its conservative execution model.  ... 
doi:10.1145/773365.773368 fatcat:cy7looedjzcgdnnewnd5bwlv3q

Levo - A Scalable Processor With High IPC

Augustus K. Uht, David Morano, Alireza Khalafi, David R. Kaeli
2003 Journal of Instruction-Level Parallelism  
The Levo high IPC microarchitecture is described and evaluated.  ...  The Tomasulo-algorithm-like broadcast buses are segmented; their lengths are constant, that is, do not increase with machine size. This helps to make Levo scalable.  ...  MIP-9708183 and EIA-9729839, the University of Rhode Island Office of the Provost, the Xilinx Corp., and the Mentor Graphics Corp. Alireza Khalafi was also supported by IBM and Compaq.  ... 
dblp:journals/jilp/UhtMKK03 fatcat:gnzlsruzpbap3iv3ed4pbiekei