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The Soft Error Problem: An Architectural Perspective

S.S. Mukherjee, J. Emer, S.K. Reinhardt
11th International Symposium on High-Performance Computer Architecture  
Acknowledgments We thank the members of the FACT (Fault Aware Computing Technology) Group for contributing to many aspects of this paper.  ...  To provide a foundation for these efforts, this paper gives a broad overview of the soft error problem from an architectural perspective.  ...  L ace is the residence cycles of ACE bits in the instructionB ace L ace × number of bits in structure --------------------------------------------------------------- The Soft Error Problem: An Architectural  ... 
doi:10.1109/hpca.2005.37 dblp:conf/hpca/MukherjeeER05 fatcat:wfhr55ejjngglhevi6n4xqdcz4

Design and analysis of an NoC architecture from performance, reliability and energy perspective

Jongman Kim, Dongkook Park, Chrys Nicopolous, N. Vijaykrishnan, Chita R. Das
2005 Proceedings of the 2005 symposium on Architecture for networking and communications systems - ANCS '05  
Our reliability exploration culminates with the introduction of an array of transient fault protection techniques, both architectural and algorithmic, to tackle reliability issues within the router's individual  ...  error protection schemes.  ...  Thus, a soft error in the SA could give rise to several packet-loss problems: (a) A soft error in the control signals might prevent the flits from traversing the crossbar in stage 2.  ... 
doi:10.1145/1095890.1095915 dblp:conf/ancs/KimPNVD05 fatcat:llfgb36ngbhbnmyxy4zicfiei4

Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective

2008 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
First, an instruction cache always stores read-only data, leading to soft error recovery by re-fetching the instructions from lower level memory.  ...  Second, the effect of the re-fetching caused by soft errors on performance is negligible. Additionally, a considerable percentage of soft errors can occur without harming the performance.  ...  Thus, the scrubbing period should be carefully selected, especially considering unrecoverable error rates. Several architectural approaches to the soft error problem were proposed recently.  ... 
doi:10.1093/ietfec/e91-a.7.1772 fatcat:53hlubrblfam7ak6b3gofgewmm

An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

Yohan Ko
2021 Electronics  
have been proposed as an attractive solution for soft error threats.  ...  The exponentially increasing occurrence of soft errors makes the optimization of reliability, performance, hardware area, and power consumption one of the main concerns in modern embedded processors.  ...  Further, ITRS lists the soft error challenge as one of the most challenging reliability problems for ground-level applications in the near future [24] .  ... 
doi:10.3390/electronics10172101 fatcat:2hvrsnnpxrgbtb2tms6uu4mkp4

Analyzing the Impact of Soft Errors in Deep Neural Networks on GPUsfrom Instruction Level

2020 WSEAS transactions on systems and control  
In particular, soft errors are the worst. Selective software­based protection solutions are among the best techniques to improve the reliability of DNNs efficiently.  ...  Moreover, we show that YOLO is more sensitive to the changes caused by soft errors than ResNet. Also, ResNet depends on the input image in its reliability, while YOLO tends to be independent.  ...  ., soft errors) cause the majority of the system fail ures [12] .  ... 
doi:10.37394/23203.2020.15.70 fatcat:cchrrxeozfduxpoccts7pxz2ie

Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective

Andreas Löfwenmark, Simin Nadjm-Tehrani
2018 Journal of systems architecture  
Dark spots on the research map of the integration problem of hardware reliability and timing predictability for multi-core avionics systems are identified.  ...  We assess the applicability of the methods to currently available multi-core processors used in avionics.  ...  Acknowledgments This work was supported by the Swedish Armed Forces, the Swedish Defence Materiel Administration and the Swedish Governmental Agency for Innovation Systems under grant nos.  ... 
doi:10.1016/j.sysarc.2018.04.001 fatcat:74tk5j6kyjfmxpufn3x7dph6ve

Architecture Building Treatments in the Mediterranean Climate From an Environmental Perspective: Case Study of Amman – Jordan

Diala Atiyat
2015 Journal of Architectural Engineering Technology  
The paper will provide the most important architecture treatments which were adopted and applied in the Mediterranean region buildings, the paper provides an analysis of the architecture elements that  ...  recommendations which can help in the design process in Mediterranean region architecture.  ...  is extraordinary. indeed, if we want to avoid the error of extracting an object from its context, by considering heritage as a series of lifeless objects, without culture or time, in stone, brick or wood  ... 
doi:10.4172/2168-9717.1000151 fatcat:qpinabawsva5rgplfpa6pylrc4

The impact of the soft errors in convolutional neural network on GPUs: Alexnet as case study

Khalid Adam, Izzeldin I. Mohd, Younis M. Younis
2021 Procedia Computer Science  
Results show that FADD and LD are the top vulnerable instructions against soft errors for Alexnet model, both instructions generate at least 84% of injected faults as SDC errors.  ...  Results show that FADD and LD are the top vulnerable instructions against soft errors for Alexnet model, both instructions generate at least 84% of injected faults as SDC errors.  ...  Conclusions In this paper, we have analyzed the error resilience of Alexnet, a well-known CNN model, from the perspective of architecture-level instructions.  ... 
doi:10.1016/j.procs.2021.02.012 fatcat:jwloam4rcbhbpncybbdmwwszzi

Phaser: Phased methodology for modeling the system-level effects of soft errors

J. A. Rivers, P. Bose, P. Kudva, J.-D. Wellman, P. N. Sanda, E. H. Cannon, L. C. Alves
2008 IBM Journal of Research and Development  
This paper presents an overview of Phaser, a toolset and methodology for modeling the effects of soft errors on the architectural and microarchitectural functionality of a system.  ...  The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept, concept, high-level design, and  ...  ., in the United States, other countries, or both.  ... 
doi:10.1147/rd.523.0293 fatcat:3ib34h73wffzfkebbhbvdtpv2y

Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability

Chang Burm Cho, Wangyuan Zhang, Tao Li
2008 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computers and Telecommunication Systems  
The increasing chip soft error rates make it is necessary to estimate process transient fault susceptibility at the microarchitecture design stage.  ...  errors) that can affect reliability.  ...  These models focus on estimating runtime soft error vulnerability for a given architecture design and are not suitable for quickly analyzing processor soft error behavior for architecture design alternatives  ... 
doi:10.1109/mascot.2008.4770557 fatcat:kkb32g34l5davpp3x5kbopeuxa

Selection of the Optimal Memory Configuration in a System Affected by Soft Errors

J.A. Maestro, P. Reviriego
2009 IEEE transactions on device and materials reliability  
The selection of the best memory configuration is a challenge for designers when systems are affected by soft errors.  ...  When memory reliability is an issue and scrubbing is not recommendable, multibit protection codes are one of the available options.  ...  Formally, the problem can be stated as follows: "Given a memory in a system suffering soft errors, characterized as {M, λ word , MT T F Target }, where M is the size in words, λ word is the event arrival  ... 
doi:10.1109/tdmr.2009.2023081 fatcat:qi7qsklitvgynfqlyjvh5z4pbu

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

Arun Arvind Nair, Lizy Kurian John, Lieven Eeckhout
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
Starting from a comprehensive study about how microarchitecture-dependent program characteristics affect soft errors, we derive the insights needed to develop an automated and flexible methodology for  ...  It is important for designers to be able to validate whether the Soft Error Rate (SER) targets of their design have been met, and help end users select the processor best suited to their reliability goals  ...  Any opinions, findings, conclusions or recommendations expressed in this paper are those of the authors and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1109/micro.2010.34 dblp:conf/micro/NairJE10 fatcat:ewityvqpdnayjipwaizpr7iksa

Efficient soft error protection for commodity embedded microprocessors using profile information

Daya Shanker Khudia, Griffin Wright, Scott Mahlke
2012 Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems - LCTES '12  
To solve the problem of detecting soft errors cheaply, we propose a profiling-based software-only application analysis and transformation solution.  ...  With smaller and cheaper transistors becoming pervasive in mainstream computing, it is necessary to protect these devices against soft errors; an increasing rate of faults necessitates the protection of  ...  Acknowledgement We thank the anonymous reviewers for their constructive comments and suggestions for improving the work.  ... 
doi:10.1145/2248418.2248433 dblp:conf/lctrts/KhudiaWM12 fatcat:e7wuhfunkfde3nc66ro3fd5yi4

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis M. Sylvester
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs.  ...  The runtimes for soft error estimation were observed to be in the order of about 1 s, compared to several minutes or even hours for previously proposed methods.  ...  they occur is called the soft error rate (SER).  ... 
doi:10.1109/tcad.2007.891036 fatcat:ipt365lsjfgxthtfismcd3tsym

Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era

Stefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone
2021 Computer Science Review  
The focus is on soft errors, which dominate the failure rate of processors in space.  ...  Error, failure and propagation models from literature are selected and employed to estimate the failure rate due to soft errors in typical processor designs.  ...  Acknowledgments This work was supported by the European Space Agency under the NPI Program, Cobham Gaisler AB, and Delft University of Technology.  ... 
doi:10.1016/j.cosrev.2020.100349 fatcat:la3jkrklerf4fff2iqu5fkhhpy
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