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Shallow Unorganized Neural Networks Using Smart Neuron Model for Visual Perception

Richard Jiang, Danny Crookes
2019 IEEE Access  
The recent success of Deep Neural Networks (DNNs) has revealed the significant capability of neural computing in many challenging applications.  ...  SUNNs have a natural topology with random interconnections, as the human brain does, and as proposed by Turing's B-type unorganized machines.  ...  Interconnections in the brain are not universally random.  ... 
doi:10.1109/access.2019.2946422 fatcat:bjtutko7kvharlel4gmkd3np2e

Shallow Unorganized Neural Networks using Smart Neuron Model for Visual Perception [article]

Richard Jiang, Danny Crookes
2019 arXiv   pre-print
The recent success of Deep Neural Networks (DNNs) has revealed the significant capability of neural computing in many challenging applications.  ...  SUNNs have a natural topology with random interconnections, as the human brain does, and as proposed by Turing's B-type unorganized machines.  ...  Interconnections in the brain are not universally random.  ... 
arXiv:1907.09050v2 fatcat:mwmfj3sbyvfjth3dhniqjjwzaa

Polymorphic On-Chip Networks

Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd Austin
2008 2008 International Symposium on Computer Architecture  
We begin this study with an area-performance analysis of the interconnect design space.  ...  Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network  ...  Acknowledgements This work has been made possible through the generous support of the Gigascale Systems Research Center, an NSF CAREER Award (ACR-0133188), Sloan Research Foundation Award (Oskin), Intel  ... 
doi:10.1109/isca.2008.25 dblp:conf/isca/KimDOA08 fatcat:xucwu54uxvdmtk2u4wu2qvhtje

Polymorphic On-Chip Networks

Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd Austin
2008 SIGARCH Computer Architecture News  
We begin this study with an area-performance analysis of the interconnect design space.  ...  Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network  ...  Acknowledgements This work has been made possible through the generous support of the Gigascale Systems Research Center, an NSF CAREER Award (ACR-0133188), Sloan Research Foundation Award (Oskin), Intel  ... 
doi:10.1145/1394608.1382131 fatcat:wrhq7u66s5hwbb4celwzeizany

Nature-inspired interconnects for self-assembled large-scale network-on-chip designs

Christof Teuscher
2007 Chaos  
In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics.  ...  Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired  ...  Addressing Interconnect Challenges by Networks-on-Chip The topic of interconnect networks for computers and chips is vast and complex.  ... 
doi:10.1063/1.2740566 pmid:17614693 fatcat:fxwyad6tevbnlbaijahvd5vgiy

A Network of Networks Approach to Interconnected Power Grids [article]

Paul Schultz, Frank Hellmann, Jobst Heitzig, Jürgen Kurths
2016 arXiv   pre-print
We present two different approaches to model power grids as interconnected networks of networks.  ...  The static glue stick construction model yields a multi-layer network from a predefined layer interconnection scheme, i.e. different layers are attached with transformer edges.  ...  ACKNOWLEDGEMENT The authors acknowledge gratefully the support of BMBF, CoNDyNet, FK. 03SF0472A.  ... 
arXiv:1701.06968v1 fatcat:nzjf6vdntvhkvjm5s6gk35dpvi

Superposition In Optical Computing

B. K. Jenkins, C. L. Giles, Pierre H. Chavel, Joseph W. Goodman, Gerard Roblin
1989 Optical Computing '88  
The property of optical superposition is considered and the implications it has in the design of computing systems is discussed.  ...  The idea is to define a finite number, M, of distinct interconnection patterns, and then assemble the interconnecting network using only these M patterns.  ...  In Fig. 2 interconnection networks. Results of this have been given in .  ... 
doi:10.1117/12.947918 fatcat:agcrgp6jsfgb3hwuvx2dl34cva

Robust Clock Network Design Methodology for Ultra-Low Voltage Operations

Mingoo Seok, David Blaauw, Dennis Sylvester
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
We also perform case studies of low voltage clock network design for a microprocessor and signal processing core.  ...  In the other case, a 3-level buffered tree is implemented, with the proposed clock tree reducing +2 skew to 2% of a clock cycle (0.68 fanout-of-4 delay) and slew variability ( ) to 0.08 at V.  ...  ACKNOWLEDGMENT The authors acknowledge the support of the Gigascale Systems Research Center, one of the five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation  ... 
doi:10.1109/jetcas.2011.2160753 fatcat:5zfwtniazfhlzlgdszz3xm5yw4

Ranking in interconnected multilayer networks reveals versatile nodes

Manlio De Domenico, Albert Solé-Ribalta, Elisa Omodei, Sergio Gómez, Alex Arenas
2015 Nature Communications  
case of standard ("monoplex") networks -- can be extended naturally to the realm of interconnected multiplexes.  ...  However, defining the centrality of actors in an interconnected structure is not trivial.  ...  A schematic of an interconnected multilayer network is shown in Fig. 1 .  ... 
doi:10.1038/ncomms7868 pmid:25904405 fatcat:ps3bmfogibdwhbdqhbw3kjdfai

Influence spread in two-layer interdependent networks: designed single-layer or random two-layer initial spreaders?

Hana Khamfroush, Nathaniel Hudson, Samuel Iloo, Mahshid R. Naeini
2019 Applied Network Science  
in the other network. 10% of nodes in layer A (chosen at random) have inter-edges to nodes in layer B (chosen at random), and vice versa. • Sparse & Designed: In this model, 8% of nodes are selected to  ...  First, we introduce the four interconnectivity cases considered in our experiments: Additionally, in the case of designed interconnectivity (Sparse-Designed or Dense-Designed), we consider how nodes are  ...  The models used for this work are outlined in full within the body of the paper. References to the random generative models used have been included in this work.  ... 
doi:10.1007/s41109-019-0150-3 fatcat:kj52pt56y5attagf62l4cuza6e

On Irregular Interconnect Fabrics for Self-Assembled Nanoscale Electronics [article]

Christof Teuscher
2006 arXiv   pre-print
Finally, the results will help to make important design decisions for building self-assembled electronics in a largely random manner.  ...  In this paper we pragmatically investigate the properties of an irregular, abstract, yet physically plausible small-world interconnect fabric that is inspired by modern network-on-chip paradigms.  ...  As opposed to the monolithic ad hoc interconnect networks used in traditional chip design, we draw inspiration from recent network-on-chip (NoC) [2] , [24] paradigms, which transmit data in the form  ... 
arXiv:cond-mat/0606584v1 fatcat:uijes4clafaqhcqri6ycjf5rri

Spatial Dispersion of Peering Clusters in the European Internet

Alessio D'Ignazio, Emanuele Giovannetti, Ph.D Cantab
2006 Social Science Research Network  
Our results show a dominance of random spatial patterns in peering agreements.  ...  We study the role played by geographical distance in the peering decisions between Internet Service Providers.  ...  The key question hence becomes: does distance play a role in determining the interconnection decisions?  ... 
doi:10.2139/ssrn.885928 fatcat:aey3wj4tr5httii4dkqcbmggnu

III Data-Center Networks [chapter]

2016 Interconnections for Computer Communications and Packet Networks  
designing interconnection networks, in a straightforward and approachable manner.  ...  So, it is no surprise that interconnection networks play an important role in almost every communications system.  ... 
doi:10.4324/9781315373485-10 fatcat:z5hwlgoopraczfykavku37onle

Design trade-offs in optoelectronic parallel processing systems using smart-SLMs

D. -T. Lu, V. H. Ozguz, P. J. Marchand, A. V. Krishnamoorthy, F. Kiamilev, R. Paturi, S. H. Lee, S. C. Esener
1992 Optical and quantum electronics  
They can also be partially folded by increasing the grain size or by reducing the randomness of the graph topology to reduce the complexity of the interconnection holograms.  ...  Physical design parameters, such as the chip size or the number of phase levels of the interconnection holograms, are related to the system design metrics such as bandwidth, volume, area and power.  ...  Fouad Kiamilev is supported by a graduate fellowship from the Office of Navel Research.  ... 
doi:10.1007/bf00619508 fatcat:lmcfe6w3ljgrlj2mq2ng7qvitm

Navigability of interconnected networks under random failures

M. De Domenico, A. Sole-Ribalta, S. Gomez, A. Arenas
2014 Proceedings of the National Academy of Sciences of the United States of America  
In this supplementary material for the paper "Navigability of interconnected networks under random failures", we extend well-known random walks to multiplexes and we introduce a new type of walk that can  ...  Finally, we show how the efficiency in exploring the multiplex critically depends on the underlying topology of layers, the weight of their inter-connections and the strategy adopted to walk.  ...  Assessing the navigability of interconnected networks (transporting information, people, or goods) under eventual random failures is of utmost importance to design and protect critical infrastructures.  ... 
doi:10.1073/pnas.1318469111 pmid:24912174 pmcid:PMC4060702 fatcat:eof5kmpkibcbnnyyfrxpevdfae
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