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The SP2 High-Performance Switch

C. B. Stunkel, D. G. Shea, B. Abali, M. G. Atkins, C. A. Bender, D. G. Grice, P. Hochschild, D. J. Joseph, B. J. Nathanson, R. A. Swetz, R. F. Stucke, M. Tsao (+1 others)
1995 IBM Systems Journal  
The heart of an IBM SP2" system is the High-Performance Switch, which is a low-latency, highbandwidth switchin network that binds together RlSC System/600 0.9 processors.  ...  The switch is constructed primarily from switching elements (the Vulcan switch chip) and adapters (the SP2 communication adapter).  ...  Acknowledgments The inspiration for, and the design and implementation of, the S P~ communication subsystem hardware is due to numerous others from IBM Research and the IBM Highly Parallel Supercomputing  ... 
doi:10.1147/sj.342.0185 fatcat:x4xgxez6rneytnoqrvolvrfbx4

MODELS AND SOLUTIONS FOR THE IMPLEMENTATION OF DISTRIBUTED SYSTEMS

Tarca Naiana, Vatuiu Teodora, Ghencea Adrian
2011 Annals of the University of Oradea: Economic Science  
The result of these technologies has enabled the evolution from centralized to distributed systems that connect a large number of computers.  ...  To enable the exploitation of the advantages of distributed systems one had developed software and communications tools that have enabled the implementation of distributed processing of complex solutions  ...  processor RISC System/6000 IBM Power Parallel Systems SPX.  ... 
doaj:334a7a0a88b34122950f076ad0c73eaf fatcat:jcyhfh3kzjfnvcnfdxpvqnayl4

High Performance Fortran Implementations: A Survey

R.H. Perrott, E. Ayguade, J. Garcia, J. Torres
1997 Scientific Programming  
It is an implementation based on subset HPF for RS/6000 SP systems and clusters of RISC system/6000 systems. It also includes extensions from outside the HPF 'standard'.  ...  alpha workstations or clusters of SMP alpha servers.  ... 
doi:10.1155/1997/875952 fatcat:pscr7dwq6rdujplescicn3yoie

Measurement, analysis and performance improvement of the Apache Web server

Yiming Hu, A. Nanda, Qing Yang
1999 1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305)  
We notice that Apache shows similar behavior on both the uniprocessor and the SMP systems.  ...  In this paper we measure and analyze the behavior of the popular Apache Web server on a uniprocessor system and a 4-CPU SMP (Symmetric Multi-Processor) system running the IBM AIX operating system.  ...  Bulent Abali at Watson helped us on setting up the test network.  ... 
doi:10.1109/pccc.1999.749447 dblp:conf/ipccc/HuNY99 fatcat:sx3sjf2zqnbxnipilq2cflcqfu

POWER3: The next generation of PowerPC processors

F. P. O'Connell, S. W. White
2000 IBM Journal of Research and Development  
Designed by IBM and deployed in various IBM RS/6000 ® systems, the superscalar RISC POWER3 processor boasts many advanced features which give it exceptional performance on challenging applications from  ...  the workstation to the supercomputer level.  ...  Acknowledgments The authors wish to thank Mike Mayfield, Steve Tung, and Dwain Hicks for helping us to understand the details of the POWER3 implementation.  ... 
doi:10.1147/rd.446.0873 fatcat:oehxzpxilrbdvk6cchi3wd5zdu

The AlphaServer 8000 Series: High-end Server Platform Development

David M. Fenwick, Denis J. Foley, William B. Gist, Stephen R. VanDoren, Daniel Wissell
1995 Digital technical journal of Digital Equipment Corporation  
The AlphaServer 8000 platform development team set aggressive system data bandwidth and memory read latency targets in order to achieve high-performance goals.  ...  The combination of industry-leading microprocessor technology and a system platform focused on low latency has resulted in a 12-processor server implementation--the AlphaServer 8400--capable of supercomputer  ...  ACKNOWLEDGMENTS Several members of the AlphaServer 8000 Development Team in addition to the authors were key contributors to the generation of this technical article.  ... 
dblp:journals/dtj/FenwickFGVW95 fatcat:dvvc5glh7vgsvluq4splcsc2cm

An analysis of operating system behavior on a simultaneous multithreaded architecture

Joshua A. Redstone, Susan J. Eggers, Henry M. Levy
2000 ACM SIGOPS Operating Systems Review  
A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.  ...  This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor.  ...  Maynard, Donnelly, and Olszewski [25] looked at a trace-driven simulation of an IBM RISC system/6000 to investigate the performance of difference cache configurations over a variety of commercial and  ... 
doi:10.1145/384264.379245 fatcat:faz5urwyovgxpgul2eokacnhxa

An analysis of operating system behavior on a simultaneous multithreaded architecture

Joshua A. Redstone, Susan J. Eggers, Henry M. Levy
2000 SIGPLAN notices  
A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.  ...  This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor.  ...  Maynard, Donnelly, and Olszewski [25] looked at a trace-driven simulation of an IBM RISC system/6000 to investigate the performance of difference cache configurations over a variety of commercial and  ... 
doi:10.1145/356989.357012 fatcat:rlpqirj5ujcexegllofqledpge

An analysis of operating system behavior on a simultaneous multithreaded architecture

Joshua A. Redstone, Susan J. Eggers, Henry M. Levy
2000 SIGARCH Computer Architecture News  
A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.  ...  This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor.  ...  Maynard, Donnelly, and Olszewski [25] looked at a trace-driven simulation of an IBM RISC system/6000 to investigate the performance of difference cache configurations over a variety of commercial and  ... 
doi:10.1145/378995.379245 fatcat:7m4rqlvgyrbvjee2b5kewta434

An analysis of operating system behavior on a simultaneous multithreaded architecture

Joshua A. Redstone, Susan J. Eggers, Henry M. Levy
2000 Proceedings of the ninth international conference on Architectural support for programming languages and operating systems - ASPLOS-IX  
A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.  ...  This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor.  ...  Maynard, Donnelly, and Olszewski [25] looked at a trace-driven simulation of an IBM RISC system/6000 to investigate the performance of difference cache configurations over a variety of commercial and  ... 
doi:10.1145/378993.379245 fatcat:lxxt65x3szh3thzef5r6umjvs4

POWER4 system microarchitecture

J. M. Tendler, J. S. Dodson, J. S. Fields, H. Le, B. Sinharoy
2002 IBM Journal of Research and Development  
The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems.  ...  The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems.  ...  The focal point for the project was in the IBM Server Group Development Laboratory in Austin, Texas, with major contributions from Server Group development laboratories in Poughkeepsie, New York, and Rochester  ... 
doi:10.1147/rd.461.0005 fatcat:2g7mipsjlrfc7cefuf23pfeg6i

Mapping, modeling, and visual exploration of structure-function relationships in the heart

R. L. Winslow, D. F. Scollan, J. L. Greenstein, C. K. Yung, W. Baumgartner, G. Bhanot, D. L. Gresh, B. E. Rogowitz
2001 IBM Systems Journal  
It is becoming clear that the emergent, integrative behaviors of biological systems result from complex interactions between all system components, and that knowledge of each component is not sufficient  ...  numerical solution of large systems of model equations, and interactive visual exploration of model dynamic behavior.  ...  Acknowledgments This work is supported by the National Institutes of Health grants RO1HL60133-01 and P50HL52307, the Whitaker Foundation, the Falk Foundation, IBM Corporation, and Physiome Sciences, Inc  ... 
doi:10.1147/sj.402.0342 fatcat:pyf6rwv3hre5basbr5sgkxsoya

Brief History of Computer Architecture Evolution and Future Trends [article]

R Groves
1995
These basic trends have been true throughout the history of computer systems and are  ...  To achieve Despite these underlying trends, the performance of computer systems has increased at a rate which technological approaches. projected to continue through the foreseeable future in the absence  ...  Applications typically run a single copy of the operating system that has been altered to exploit parallelism and to (SMPs).  ... 
doi:10.5170/cern-1995-005.147 fatcat:54fhr5g7qbdf7ebmupzhistkqy

New algebraic formulation of density functional calculation

Sohrab Ismail-Beigi, T.A. Arias
2000 Computer Physics Communications  
This article addresses a fundamental problem faced by the ab initio community: the lack of an effective formalism for the rapid exploration and exchange of new methods.  ...  ab initio techniques to the derivation and transcription of a few lines of algebra.  ...  The code development was carried out on the MIT Xolas prototype SMP cluster as well as the MIT Pleiades Alpha cluster.  ... 
doi:10.1016/s0010-4655(00)00072-2 fatcat:wtuazlezmbezvmiupnvetb5iqm

DB2 Parallel Edition

C. K. Baru, G. Fecteau, A. Goyal, H. Hsiao, A. Jhingran, S. Padmanabhan, G. P. Copeland, W. G. Wilson
1995 IBM Systems Journal  
However, the current generation of massively parallel processor systems, such as the IBM Scalable PowERparallel Systems* (the s P l * and S P~* class of systems), are much more robust and easier to use  ...  Single-system (or serial) DBMSS can-, not handle the capacity and the complexity requirements of these applications.  ...  This implies that a shared-memory system can support less than 10 RISC System/6000* processors of the current generation accessing the shared memory at the same time.  ... 
doi:10.1147/sj.342.0292 fatcat:3mso35ij6bd6jk3sgrbashfrme
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