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The PowerPC 603 microprocessor: performance analysis and design trade-offs
Proceedings of COMPCON '94
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Performance modeling was used in conjunction with application CO& traces to tune the PowerPC 603 microprocessor desiga This modeling technique albwed the design space to be constrained by performance, ...
examined with high confidence of performance. Sampled traces provided a f a turnaround for evaluation of the design space. ...
Figure 1: 603 Performance Analysis Tbe 603 performance model was refined and validated as design matured by comparing it to the actual design. ...
doi:10.1109/cmpcon.1994.282893
dblp:conf/compcon/PoursepanjOBGDLSP94
fatcat:zghtgppzjrcatarqefcqvxlc6e
Resource allocation in a high clock rate microprocessor
1994
SIGPLAN notices
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This paper discusses the design of a high clock rate (300MHz) processoc The architecture is described, and the goals for the design are explained. ...
A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. ...
Acknowledgments The authors would like to thank the other members of Aurora group: Dave Futti, Dave Kibler, Patrick Sherhart, Ajay Chandna, Tim Stanley, and Dave Nagle. ...
doi:10.1145/195470.195510
fatcat:nxe755kxezgb7n7gizjg7czezm
Resource allocation in a high clock rate microprocessor
1994
Proceedings of the sixth international conference on Architectural support for programming languages and operating systems - ASPLOS-VI
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This paper discusses the design of a high clock rate (300MHz) processoc The architecture is described, and the goals for the design are explained. ...
A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. ...
Acknowledgments The authors would like to thank the other members of Aurora group: Dave Futti, Dave Kibler, Patrick Sherhart, Ajay Chandna, Tim Stanley, and Dave Nagle. ...
doi:10.1145/195473.195510
dblp:conf/asplos/UptonHMB94
fatcat:4hv2xqb2mfhhzkgsjtcjrwd3dq
Resource allocation in a high clock rate microprocessor
1994
ACM SIGOPS Operating Systems Review
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This paper discusses the design of a high clock rate (300MHz) processoc The architecture is described, and the goals for the design are explained. ...
A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. ...
Acknowledgments The authors would like to thank the other members of Aurora group: Dave Futti, Dave Kibler, Patrick Sherhart, Ajay Chandna, Tim Stanley, and Dave Nagle. ...
doi:10.1145/381792.195510
fatcat:j3qgqe6cbfafphvaqoyjrchmg4
Performance evaluation of the PowerPC 620 microarchitecture
1995
SIGARCH Computer Architecture News
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The PowerPC 620TM microprocessor' is the most recent and performance leading member of the PowerPCT~i family. ...
The 64-bit PowerPC 620 microprocessor employs a two-phase branch prediction scheme, dynamic renaming for all the register jiles, distributed multi-entry reservation stations, true out-oforder execution ...
The second, lowpower chip, is the PowerPC 603 microprocessor [19] . Recently, a more advanced chip for desktop systems has begun production, the PowerPC 604TM microprocessor [20] . ...
doi:10.1145/225830.224417
fatcat:tiiodeg7zbeyhmzrlrxvv22i2q
Performance evaluation of the PowerPC 620 microarchitecture
1995
Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95
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The PowerPC 620TM microprocessor' is the most recent and performance ...
The second, lowpower chip, is the PowerPC 603 microprocessor [19] . Recently, a more advanced chip for desktop systems has begun production, the PowerPC 604TM microprocessor [20] . ...
POWER Architecture, PowerPC, PowerPC Architecture, PowerPC 601, PowerPC 603, PowerPC 604, PowerPC 620, and RISC System /6000 are trademarks of IBM. ...
doi:10.1145/223982.224417
dblp:conf/isca/DiepNS95
fatcat:lnwu6clhffazjkzncnzlsfyrmi
A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS
2008
2008 IEEE Asian Solid-State Circuits Conference
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The design relies on high residency in a new low-power state in order to keep average power and idle power below 220 and 80 mW, respectively. ...
The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution ...
ACKNOWLEDGMENT The authors gratefully acknowledge the support of Intel's Ultra-Mobility-Group Vice-President Elenora Yoeli and the work of the talented and dedicated Intel design and product teams in Austin ...
doi:10.1109/asscc.2008.4708718
fatcat:s75igiqee5elva2crdciwgk2zi
Generating FPGA-Accelerated DFT Libraries
2007
15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)
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The partitioning strategy is a heuristic based on the DFT's divide-and-conquer algorithmic structure and fine tuned by the feedback-driven exploration of candidate designs. ...
We present evaluations of hardware-software DFT implementations running on the embedded PowerPC processor and the reconfigurable fabric of the Xilinx Virtex-II Pro FPGA. ...
Acknowledgment This work was supported by DARPA through the Department of Interior grant NBCH1050009 and by NSF through awards 0234293 and 0325687. ...
doi:10.1109/fccm.2007.58
dblp:conf/fccm/DAlbertoMSFHMPJ07
fatcat:ffuoaygm6fcn5guzlhwmjamubq
Leveraging Wire Properties at the Microarchitecture Level
2006
IEEE Micro
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All energy and energy-delay values are normalized with respect to Model 1. Energy-delay is computed by multiplying total processor energy by number of executed cycles. ...
In addition to this basic latency-bandwidth trade-off, we can leverage the latencypower trade-off by introducing the option of transferring data on slower, power-efficient wires. ...
The hardware required to detect narrow-bit-width data is easy to implement-the PowerPC 603, for example, has hardware for detecting the number of leading zeros; it then uses this value to determine latency ...
doi:10.1109/mm.2006.123
fatcat:jggzbzgnxnbrlnnqpnko7xjtbq
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance
2000
ACM Transactions on Computer Systems
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Overall, these optimizations highlight an increasing opportunity for value-based optimizations to improve both power and performance in current microprocessors. ...
The large address space needs of many current applications have pushed processor designs toward 64-bit word widths. ...
The reason for choosing the 16-bit mark is more arbitrary and reflects the need to balance two trade-offs in the selection of the boundary at which to clock gate. ...
doi:10.1145/350853.350856
fatcat:ztn256zwcvahnchyjskwuhyxw4
Power Analysis and Optimization Techniques for Energy Efficient Computer Systems
[chapter]
2005
Advances in Computers
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Reducing power consumption has become a major challenge in the design and operation of today's computer systems. ...
and software during design time. ...
The PowerPC 603 processor supports several sleep modes based on clock gating. For this purpose, it has two types of clock controllers: global and local. ...
doi:10.1016/s0065-2458(04)63004-x
fatcat:qqgqxgtgerh3dikj3khtzmysqe
Reducing processor power consumption by improving processor time management in a single-user operating system
1996
Proceedings of the 2nd annual international conference on Mobile computing and networking - MobiCom '96
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The CPU is one of the major power consumers in a portable computer, and considerable power can be saved by turning off the CPU when it is not doing useful work. ...
These techniques include turning off the processor when all processes are blocked, turning off the processor when processes appear to be busy waiting, and extending real time process sleep periods. ...
] for the PowerPC 603, and by Suzuki and Uno [15] in a 1993 patent. ...
doi:10.1145/236387.236437
dblp:conf/mobicom/LorchS96
fatcat:2kl5hlcwknbo3lzqfiwgwpetua
The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements
2007
IEEE Journal of Solid-State Circuits
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This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy-delay metric. ...
The analysis in the energy-delay space allows us to understand some intuitive design choices in a quantitative way and to identify the optimal storage element topologies for an arbitrary system specification ...
ACKNOWLEDGMENT The authors would like to thank B. Zeydel for his suggestions on adder and pipeline stage design. ...
doi:10.1109/jssc.2007.896516
fatcat:nqnjj63blnd5jevxwfkmoxlskq
Modeling and Characterizing Power Variability in Multicore Architectures
2007
2007 IEEE International Symposium on Performance Analysis of Systems & Software
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The impact of random variation in physical factors such as gate length and interconnect spacing will have a profound impact on not only performance of chips, but also their power behavior. ...
Despite the large impact that power variability will have on future designs, there is a lack of published work that examines architectural implications of this phenomenon. ...
Acknowledgments We would like to thank the anonymous reviewers for their constructive feedback and helpful suggestions. This work was supported in part by NSF award CCF-0541337. ...
doi:10.1109/ispass.2007.363745
dblp:conf/ispass/MengHJI07
fatcat:miphfyj3dbhlnpkak3aq2uauxq
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
2006
SIGARCH Computer Architecture News
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On-chip wires can be designed to have different latency, bandwidth, and energy properties. Likewise, coherence protocol messages have different latency and bandwidth needs. ...
In future technologies, communication between different L1s will have a significant impact on overall processor performance and power consumption. ...
These wire properties provide an opportunity to design wires that trade off bandwidth and latency. ...
doi:10.1145/1150019.1136515
fatcat:bgwm4pvcm5dkpioicrordsh5fa
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