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A Hardware/Software Co-design and Co-verification on a Novel Embedded Object-Oriented Processor [chapter]

Chi Hang Yau, Yi Yu Tan, Pak Lun Mok, Wing Shing Yu, Anthony S.Fong
2005 Lecture Notes in Computer Science  
A novel objectoriented processor offers an opportunity to enhance the system security, performance and provides a more effective way to manipulate OOP instead of using a software Virtual Machine. jHISC  ...  is a novel object-oriented processor which provides a natural way to map the concept of OOP into architectural level through the hardware object data structure.  ...  Acknowledgements The work described in this paper was partially supported by a grant from City University of Hong Kong (Strategic Research Grant Project No. 7001548).  ... 
doi:10.1007/11596356_39 fatcat:g4dilz75bvc4pg762dh5ffbdji

Ally: OS-Transparent Packet Inspection Using Sequestered Cores

Jen-Cheng Huang, Matteo Monchiero, Yoshio Turner, Hsien-Hsin S. Lee
2011 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems  
Ally maintains a copy of each descriptor queue in DPI memory and configures the NIC to use these queues (DPI queues) instead of the descriptor queues in OS memory (OS queues) through configuring the base  ...  The accesses that need to be redirected include accesses to the base pointers of the descriptor queues and the Tail/Head registers of each queue.  ... 
doi:10.1109/ancs.2011.11 dblp:conf/ancs/HuangMTL11 fatcat:2lcxqtwi4bb4ph322tn235csmy

An MPI Implementation on the Top of the Virtual Interface Architecture [chapter]

Massimo Bertozzi, Franco Boselli, Gianni Conte, Monica Reggiani
1999 Lecture Notes in Computer Science  
The Virtual Interface architecture The basic concepts that have been used for the VIA design are the following: -the process has to execute a small number of operations for starting, ending, or managing  ...  The Virtual Interface Architecture (VIA) is an emerging standard designed by Intel, Microsoft, and Compaq aimed at the reduction of communication latency for cluster of workstations or system area networks  ...  The VIA based LAM-MPI implementation is freely downloadable from: http://www.ce.unipr.it/pardis/parma2/.  ... 
doi:10.1007/3-540-48158-3_25 fatcat:dozfpz3zrzdwffd4or4yrjfsoq

A Virtualization Based Monitoring System for Mini-intrusive Live Forensics

Xianming Zhong, Chengcheng Xiang, Miao Yu, Zhengwei Qi, Haibing Guan
2013 International journal of parallel programming  
In this paper, we propose VAIL, a novel virtualization based monitoring system for miniintrusive live forensics, which employs hardware assisted virtualization technique to gather integrated information  ...  Meanwhile, the execution of the target system will not be interrupted and VAIL keeps immune to attacks from the target system.  ...  As shown in Figure 3 , the base address of the descriptor ring is stored in register Transmit Descriptor Base Address (TDBA)/Receive Descriptor Base Address (RDBA), while the total length is saved in  ... 
doi:10.1007/s10766-013-0285-2 fatcat:43fmjflmybdxbiiuao7vhccjdq

High-throughput coherence control and hardware messaging in Everest

A. K. Nanda, A.-T. Nguyen, M. M. Michael, D. J. Joseph
2001 IBM Journal of Research and Development  
The results show that the features of the Everest architecture can have significant impact on the performance of distributed shared-memory servers.  ...  Everest is an architecture for high-performance cache coherence and message passing in partitionable distributed shared-memory systems that use commodity shared multiprocessors (SMPs) as building blocks  ...  He is currently involved in several research projects at IBM, including MemorIES (Memory Instrumentation and Emulation System), High Throughput Coherence Controllers, and the Watson Commercial Server Performance  ... 
doi:10.1147/rd.452.0299 fatcat:smlewcsijzg6li5ezb5ydrbvye

Infiniband scalability in Open MPI

G.M. Shipman, T.S. Woodall, R.L. Graham, A.B. Maccabe, P.G. Bridges
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Open MPI, a new open source implementation of the MPI standard targeted for production computing, provides several mechanisms to enhance Infiniband scalability.  ...  Initial comparisons with MVAPICH, the most widely used Infiniband MPI implementation, show similar performance but with much better scalability characteristics.  ...  This material is based upon work supported by Subcontract No. 12783-001-05 49 issued to Rice University from the Regents of the University of California (Los Alamos National Laboratory).  ... 
doi:10.1109/ipdps.2006.1639335 dblp:conf/ipps/ShipmanWGMB06 fatcat:hvqoli2kanevnhnycaqrm2prcy

Architectural considerations for CPU and network interface integration

C.D. Cranor, R. Gopalakrishnan, P.Z. Onufryk
2000 IEEE Micro  
In such designs the DMA controller often becomes the most complex part of the system.  ...  The popularity of the Internet and the emergence of broadband access networks is fueling the development of communications processors -devices that integrate processing, networking, and system functions  ...  The system architecture of a communications processor based on UNUM is shown in Figure 3 . The CPU core interfaces to the rest of the system through an Internal Bus Interface Unit (IBIU).  ... 
doi:10.1109/40.820048 fatcat:uilusghauvgudfb5gejpeckxki

Bringing Virtualization to the x86 Architecture with the Original VMware Workstation

Edouard Bugnion, Scott Devine, Mendel Rosenblum, Jeremy Sugerman, Edward Y. Wang
2012 ACM Transactions on Computer Systems  
As a result, VMware Workstation had to deal with new challenges associated with (i) the lack of virtualization support in the x86 architecture, (ii) the daunting complexity of the architecture itself,  ...  systems, and applications, none of them asking for virtualization.  ...  The use of segmentation-based protection eliminated most of the overheads traditionally associated with system-level dynamic binary translation.  ... 
doi:10.1145/2382553.2382554 fatcat:zmbouiju6rhxxaenuur67bjgw4

Rule-Based Integrity Checking of Interrupt Descriptor Tables in Cloud Environments [chapter]

Irfan Ahmed, Aleksandar Zoranic, Salman Javaid, Golden Richard, Vassil Roussev
2013 IFIP Advances in Information and Communication Technology  
In this scenario, multiple virtual machines (VMs) run the same version of an operating system kernel, which implies that IDT-related code should also be identical across the pool of VMs.  ...  An interrupt descriptor table (IDT) is used by a processor to transfer the execution of a program to software routines that handle interrupts raised during the normal course of operation or to signal an  ...  The current version of IDTchecker performs one-to-one matching and can be enhanced using this approach.  ... 
doi:10.1007/978-3-642-41148-9_21 fatcat:olgk7srcqbcwhcna6snulhpbii

Virtual-Threading: Advanced General Purpose Processors Architecture [article]

Andrei I. Yafimau
2009 arXiv   pre-print
The key elements of the architecture are 1) the distributed fine grain representation of the architectural register file, which elements are hardware swapped through levels of a microarchitectural memory  ...  This architecture originates a processor virtualization in the direction of activities virtualization, which is orthogonal to the well-known direction of memory virtualization.  ...  by means of an ISA code just as the pages swapping was performed in the early virtual memory systems.  ... 
arXiv:0910.4052v1 fatcat:jvjjjf5h55g5xaexkc2cqbtdfu

Enhancing Programmability, Portability, and Performance with Rich Cross-Layer Abstractions [article]

Nandita Vijaykumar
2019 arXiv   pre-print
Second, as a hardware/system designer, architecting faster and more efficient systems is challenging as the vast majority of the program's semantic content gets lost in translation with today's hardware-software  ...  First, significant effort and expertise are required to write high-performance code to harness the full potential of today's diverse and sophisticated hardware.  ...  We evaluate and demonstrate the performance bene ts of Locality Descriptors from e ectively leveraging di erent types of reuse-based locality in the cache hierarchy and NUMA locality in a NUMA memory system  ... 
arXiv:1911.05660v1 fatcat:w5f3g4isqbcphm2jjfzjtvrjnq

A Java processor with hardware-support object-oriented instructions

Tan Yiyu, Lo Wan Yiu, Yau Chi Hang, Richard Li, Anthony S. Fong
2006 Microprocessors and microsystems  
well with the essential requirements of memory-constraint embedded devices, such as real-time operations and low power consumptions.  ...  Among the current hardware or software solutions to the Java virtual machine, the object-oriented related Bytecodes are implemented by software traps or microcode, and their performance does not match  ...  Acknowledgements This work has been supported by the Strategic Research Grant 7001847 of the City University of Hong Kong.  ... 
doi:10.1016/j.micpro.2005.12.007 fatcat:g5yz5st44nccbfco6kjlsiie2y

Design and implementation of a user-level Sockets layer over Virtual Interface Architecture

Jin-Soo Kim, Kangho Kim, Sung-In Jung, Soonhoi Ha
2003 Concurrency and Computation  
Our objective is to use the SOVIA layer to accelerate the existing Sockets-based applications with a reasonable effort and to provide a portable and high-performance communication library based on VIA  ...  The Virtual Interface Architecture (VIA) is an industry standard user-level communication architecture for system area networks.  ...  Enhancing portability It is one of our goals to enable application programs written for the Sockets API to take advantage of the high performance of VIA seamlessly through the SOVIA layer.  ... 
doi:10.1002/cpe.721 fatcat:ocdatxoq2nhnlobkl57tcadfqe

MOPED: Orchestrating interprocess message data on CMPs

Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
In this paper, we describe a Message Orchestration and Performance Enhancement Device (MOPED) that provides hardware mechanisms to support state-of-the-art message passing protocols such as MPI.  ...  MOPED thus allows full overlap between communication and computation on the cores. We extended a 16-core full-system simulator based on Simics and FeS2.  ...  Beckman Research Award, the Information Trust Institute of the University of Illinois at Urbana-Champaign, and the Hewlett-Packard Company through its Adaptive Enterprise Grid Program.  ... 
doi:10.1109/hpca.2011.5749721 dblp:conf/hpca/GuLKS11 fatcat:l2ca6frrmzgv7ockyr7l6zrzrq

Zikimi: A Case Study in Micro Kernel Design for Multimedia Applications

Sang-Yeob Lee, Youjip Won, Whoi-Yul Kim
2005 Multimedia tools and applications  
The result of performance experiment shows that LMS (linear memory system) of Zikimi micro kernel achieves significant performance improvement on memory allocation against legacy virtual memory management  ...  We use the skeleton of existing Linux operating system and develop a micro-kernel to perform a number of specific tasks efficiently and effectively.  ...  Virtual memory system gives good system performance boost by abstracting primary and secondary storage space into one single large virtual primary memory space.  ... 
doi:10.1007/s11042-005-3813-2 fatcat:4n3p3uzb5bhrplqpgtpijg5kuy
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