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Sequential Element Design With Built-In Soft Error Resilience
2006
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). ...
Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. ...
ACKNOWLEDGMENT The authors would like to thank K. Ganesh, J. Maiz, P. Shipley, A. Vo, S. Walstra, and V. ...
doi:10.1109/tvlsi.2006.887832
fatcat:ou57qel25ren7p7yxoo2eadgva
A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems
[article]
2022
arXiv
pre-print
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The Through silicon via based 3D Network on chip is the prospective solution for integrating many cores on single die. ...
The article presents an elaborate discussion on fault models, failure mechanisms, resilient 3D routers, defect tolerance methods for the TSV based 3D NOC many-core systems. ...
Tullsen et al. proposed Simultaneous multithreading (SMT) [5] , is a technique that process one or more hardware threads concurrently by dividing the resources amongst threads dynamically (e.g., register ...
arXiv:2203.07830v1
fatcat:dsbx3o4v3femhi5d6kfrurzuoi
Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware
2015
2015 11th European Dependable Computing Conference (EDCC)
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We run synthetic benchmarks and system benchmarks to evaluate the performance overhead of the approach, observe that the overhead varies based on the characteristics of workloads and the variants (LC-RCoE ...
words maximum: (PLEASE TYPE) The thesis presents microkernel-based software-implemented mechanisms for improving the trustworthiness of computer systems based on commercial off-the-shelf (COTS) hardware ...
The R-unit (a register file) is protected by ECC and also stores the architecture checkpoint used for recovery. Caches are guarded by parity. ...
doi:10.1109/edcc.2015.16
dblp:conf/edcc/ShenE15
fatcat:xq65e72x7zcnjbbmrwpgebqnxa
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software
2016
Proceedings of the IEEE
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We conclude with an outlook for the emerging field. ...
We focus on computing devices and their design at various levels to combat variability. ...
A variable-latency technique alleviates the impact of the process variations on the register file and the execution units in a microprocessor [32] . ...
doi:10.1109/jproc.2016.2518864
fatcat:sxrsu3excbdg5p7sk4iczz262y