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The PDP-11 virtual machine architecture

Gerald J. Popek, Charles S. Kline
1975 Proceedings of the fifth symposium on Operating systems principles - SOSP '75  
NFP[, HFPD.Samples of the causes of difficulties encountered while developing the PDP-11/qS virtual machine architecture folios. ugh the use of a bit in the PSU. ghee that bit is set by loading the PSW  ...  as part o~ a case study of the unknown troubles mhich can await one who attempts to adapt ah architecture for a task not included in its initial design, the experiences are instructive  ... 
doi:10.1145/800213.806527 dblp:conf/sosp/PopekK75 fatcat:hfkhzdyrd5eqzonwflpyovbmra

A Case Study Of Computer Emulation*

T.A. Marsland, J.C. Demco
1978 INFOR. Information systems and operational research  
Through the design and construction of an emulator for DEC PDP-11 computers, the extent to which the Nanodata QM-f can serve as a universal host is being explored.  ...  RESUME Par le design et la construction d'un emulateur pour les ordinateurs PDP-11, les auteurs examinent la possibilite de se servir du Nanodata QM-1 comme hSte universel.  ...  ACKNOWLEDGMENTS The repeated discussions with S. Sutphen, regarding the hardware features of the PDP-11 and QM-1 computers, are much appreciated and helped reduce the inaccuracies in this study.  ... 
doi:10.1080/03155986.1978.11731695 fatcat:cuieh3rya5crvfnlwal5silrza

PdP

Yong Liao, Dong Yin, Lixin Gao
2009 Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures - VISA '09  
This paper presents PdP, a flexible virtual network platform which can achieve high speed packet processing. A PdP node has a cluster of machines that can perform packet processing in parallel.  ...  Both the control plane and the data plane of a virtual network run in virtual machines so as to be isolated from other virtual networks.  ...  ACKNOWLEDGEMENTS The authors are grateful to the anonymous reviewers for the many helpful comments and suggestions. This work is partially supported by U.S. NSF grants CNS-0626618 and CNS-0831940.  ... 
doi:10.1145/1592648.1592651 dblp:conf/sigcomm/LiaoYG09 fatcat:ldfl7xz35ffzvn7ee537cevnfq

Implications of structured programming for machine architecture

Andrew S. Tanenbaum
1978 Communications of the ACM  
Based on an empirical study of more than 10,000 lines of program text written in a GOTO-less language, a machine architecture specifically designed for structured programs is proposed.  ...  As a consequence, instruction decoding time is minimized, and the machine is efficient with respect to both space and time.  ...  The proposed machine, which we shall call EM-1 (Experimental Machine-l) has a paged, segmented virtual memory.  ... 
doi:10.1145/359361.359454 fatcat:jc4j7n5b75hstkrkffytvn2bg4

Formal properties of recursive Virtual Machine architectures

Gerald Belpaire, Nai-Ting Hsu
1975 Proceedings of the fifth symposium on Operating systems principles - SOSP '75  
A formal model of hardware/software architectures is developed and applied to Virtual Machine Systems.  ...  Results are derived on the sufficient conditions that a machine architecture must verify in order to support VM systems.  ...  In particular, the study of VM systems has uncovered interesting relations between the software structure and the host machine architecture.  ... 
doi:10.1145/800213.806526 dblp:conf/sosp/BelpaireN75 fatcat:732kn4etpfbglnyb3xsyynjode

Low-latency privacy-enabled Context Distribution Architecture

Joao M. Goncalves, Diogo Gomes, Rui Aguiar
2012 2012 IEEE International Conference on Communications (ICC)  
After describing the enhancements to the architecture, a prototype of the system is presented.  ...  In this paper the authors present an extension to this architecture that allows for the introduction of a complex degree of access control in context distribution.  ...  ACKNOWLEDGMENT The work presented in this paper was partially supported by the European Comission via the ICT FP7 SOCIETIES Integrated Project (No. 257493) [19] .  ... 
doi:10.1109/icc.2012.6364027 dblp:conf/icc/GoncalvesGA12 fatcat:pj7layopdfa7touqxfnx6ggzhq

Initial selection and screening of the CFA candidate computer architectures

Samuel H. Fuller, Harold S. Stone, William E. Burr
1977 Proceedings of the June 13-16, 1977, national computer conference on - AFIPS '77  
for the more intensive evaluation discussed in the companion articles.4,6,S The machines selected by this initiai ranking and sl:reening process for runher evaiuation were the Interdata 8/32, DEC PDP-II  ...  These initial criteria were used in this first phase of the CF A evaluation process to reduce the number of computer architectures from the original set of nine to the most promising three or four architectures  ...  If an architecture fails this definition it may still support virtual machines in a more limited sense.  ... 
doi:10.1145/1499402.1499433 dblp:conf/afips/FullerSB77 fatcat:jitsvuhl6ncpbbaplisv3wxpmm

Industrial Data Space Architecture Implementation Using FIWARE

Álvaro Alonso, Alejandro Pozo, José Cantera, Francisco de la Vega, Juan Hierro
2018 Sensors  
We validate the proposed architecture by deploying and testing it in a real industry use case that tries to improve the maintenance and operation of milling machines.  ...  In this scope, the Industrial Data Spaces (IDS) Association has created a Reference Architecture model that aims to provide a common frame for designing and deploying Industry IoT infrastructures.  ...  Acknowledgments: Authors would like to thank the contribution of Innovalia and +GF+, that have provided the data and infrastructure for performing the experiments.  ... 
doi:10.3390/s18072226 pmid:29997317 pmcid:PMC6068996 fatcat:rivy466dbrdoxj46goe4di4zl4

Deep dyslexia: A case study of connectionist neuropsychology

David C. Plaut, Tim Shallice
1993 Cognitive Neuropsychology  
In any case, the area requires further empirical study and simulations.  ...  Lexical decision was "surprisingly good" for 9 of the 11 cases listed by Coltheart (1980a) for which there was data.  ... 
doi:10.1080/02643299308253469 fatcat:3uqyq5nxtzabdgith5cbcdpvpu

Using cache memory to reduce processor-memory traffic

James R. Goodman
1983 SIGARCH Computer Architecture News  
Cache memory is investigated as a way to reduce the memory-processor traffic.  ...  We argue that such an environment is possible if the traffic to backing store is small enough that many processors can share a common memory and if the cache data consistency problem is solved.  ...  Smith for providing the PDP-11 trace tapes upon which much of our early work depended. We also wish to thank T.-H. Yang for developing the VAX trace facility. P. Vitale and T.  ... 
doi:10.1145/1067651.801647 fatcat:nbgoz7jphncj7ouiemgufa74iu

Multiprocessor Architectures For Concurrent Programs

Per Brinch Hansen
1978 Proceedings of the 1978 annual conference on - ACM 78  
generates virtual codẽ~~ a stack machine .  ...  is executed directly by sicroprograms , then it should be slightly faster than the interpreted code on the PDP 11/45.  ... 
doi:10.1145/800127.804119 dblp:conf/acm/Hansen78 fatcat:ygywdgi7wreblbtfyql6rzu3rm

RISC I

David A. Patterson, Carlo H. Sequin
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
corresponding architectural design, a machine wrth a high effective throughput can be achieved.  ...  In addition, such a machine should have a much shorter design trme. This paper presents the architecture of RISC I and its novel hardware support scheme for procedure call/return.  ...  The RISC Project has been sustained by a large number of students. We would like to thank all those in the Berkeley community who have helped to push RISC from a concept to an engineering experiment.  ... 
doi:10.1145/285930.285981 dblp:conf/isca/PattersonS98a fatcat:zt4t2qeaybgbnlmhsemzxc345i

Multiprocessor architectures for concurrent programs

Per Brinch Hansen
1978 SIGARCH Computer Architecture News  
generates virtual codẽ~~ a stack machine .  ...  is executed directly by sicroprograms , then it should be slightly faster than the interpreted code on the PDP 11/45.  ... 
doi:10.1145/641829.641830 fatcat:3vzaddij5fhwhl2rvcakisfopm

Migrating to Zero Trust Architecture: Reviews and Challenges

Songpon Teerakanok, Tetsutaro Uehara, Atsuo Inomata, Qi Li
2021 Security and Communication Networks  
a resource to the subject without relying on implicit trust.  ...  Unlike the perimeter-based architecture in which any subject behind the wall (i.e., inside the predefined perimeter) is considered trusted, zero trust architecture (ZTA) processes any request and provides  ...  A Case Study of Google's BeyondCorp. An excellent example of ZTA implementation is Google's BeyondCorp.  ... 
doi:10.1155/2021/9947347 fatcat:bergzmag5fddzgplxyegnmleke

A VMM security kernel for the VAX architecture

P.A. Karger, M.E. Zurko, D.W. Bonin, A.H. Mason, C.E. Kahn
1990 Proceedings. 1990 IEEE Computer Society Symposium on Research in Security and Privacy  
This paper describes the development of a virtual-machine monitor (VMM) security kernel for the VAX architecture.  ...  The VAX security kernel supports multiple concurrent virtual machines on a single VAX system, providing isolation and controlled sharing of sensitive data.  ...  An initial design study [17] concluded in 1982 that such a security kernel would be practical for the VAX architecture. The secnrit y kernel was initially prototype on a VAX-11/730 system.  ... 
doi:10.1109/risp.1990.63834 dblp:conf/sp/KargerZBMK90 fatcat:sxir3rrvlfehrea4atviaamyfa
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