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FileSyncer: Design, Implementation, and Performance Evaluation

Oluwafemi Osho, Anthony Ugbede Faruna
2016 International Journal of Computer Network and Information Security  
This paper presents the design, implementation, and evaluation of FileSyncer, a rapid and efficient file synchronization tool that, in addition to the traditional synchronization capabilities, supports  ...  manual update selection and mechanism to revert a synchronization process back to the last previous state.  ...  The system design, implementation and testing, and evaluation of the performance of the system are covered in sections six, seven, and eight in the order given.  ... 
doi:10.5815/ijcnis.2016.11.04 fatcat:tbrbjvsuzrbmnnnpovd3uhvs7u

FPGA Implementation of High Performance and Low Power VOD Server

Qiang Cao, Jiang Jiang, Chang Wang, Yongxin Zhu
2014 International Journal of Future Computer and Communication  
Besides, we propose a dynamic file chunking technique to implement real time playing. With it, users can interact with the system when playing a video. Index Terms-VOD, FPGA, architecture, low power.  ...  In this paper, we describe the structure of the VOD system, the method of processing requests and the organization of large amounts of information.  ...  Parameter type description connection id uint32 identify of the TCP connection, generated by TCP/IP module request file name char[12] the multimedia file name on command, assume maximum length  ... 
doi:10.7763/ijfcc.2014.v3.286 fatcat:ahr2wa2njnf3rhptwy3emov3ki

Fpga Implementation Of 16 Bit Risc Cpu And Performance Analysis

DINESH B BORUDE
2017 Zenodo  
In this paper, authors have design, implement and performance analysis of a 16-bit Reduced Instruction Set (RISC) CPU using XILINX tool.  ...  The processor includes the ALU, Shifter, Register array, Instruction register, program counter, address register, Operand register, Comparator and Control unit.  ...  It expresses the performance of an electronic system, from which the physical circuit or system can be implemented.  ... 
doi:10.5281/zenodo.1466625 fatcat:3vtfwrdfkzdxxd4hbcoz7gg3u4

Zero Configuration Networking: Implementation, performance, and security

Farhan Siddiqui, Sherali Zeadally, Thabet Kacem, Scott Fowler
2012 Computers & electrical engineering  
We compare two popular implementations of Zeroconf namely, Avahi and Mono.Zeroconf running on Linux and Windows XP operating systems respectively.  ...  We further investigate the performance of the IP Security (IPSec) protocol when used by our Mono.Zeroconf implementation running on the Windows XP platform.  ...  In section 4, we discuss details of our Zeroconf implementation, followed by sections 5 and 6 which present the performance analysis of the two Zeroconf implementations namely, Avahi and Mono.Zeroconf.  ... 
doi:10.1016/j.compeleceng.2012.02.011 fatcat:mcybdvui5fdnhfbmt5n7mo6qby

The Warp Computer: Architecture, Implementation, and Performance

Marco Annaratone, Emmanuel Arnould, Thomas Gross, H. T. Kung, Monica Lam, Onat Menzilcioglu, Jon A. Webb
1987 IEEE transactions on computers  
We have implemented application programs in many areas, This paper describes the architecture, implementation, and including low-level vision for robot vehicle navigation, image performance of the Warp  ...  This paper describes the architecture of the Warp machine, The Warp machine is an attached processor to a general the rationale of the design and the implementation, and purpose host running the Unix operating  ...  register file used in the computation of the data set.  ... 
doi:10.1109/tc.1987.5009502 fatcat:xup2rwwivjb2jfjnb3fhiwgv7i

The implementation and performance of compressed databases

Till Westmann, Donald Kossmann, Sven Helmer, Guido Moerkotte
2000 SIGMOD record  
Our benchmark results demonstrate that compression indeed offers high performance gains (up to 50%) for IOintensive queries and moderate gains for CPU-intensive queries.  ...  We will present such light-weight compression techniques and give the results of running the TPC-D benchmark on a so compressed database and a non-compressed database using the AODB database system, an  ...  the UNIX gzip and the DOS zip commands that we use to ship files across the Internet and to store large files and software packages that we do not need very often.  ... 
doi:10.1145/362084.362137 fatcat:uzxnvmsw6fc5djhryzeapqomhu

Network Connectivity Proxy: Architecture, Implementation, and Performance Analysis

Raffaele Bolla, Maurizio Giribaldi, Rafiullah Khan, Matteo Repetto
2017 IEEE Systems Journal  
Performance evaluation was conducted in a synthetic scenario, where fake clients registered a set of behavioral rules with the NCP and notified power state transitions.  ...  Section V lists some of the most relevant issues that arose during the implementation and evaluation of the software; it also reports performance evaluation of the NCP software.  ...  He is currently a Full Professor with the Department of Electrical, Electronic and Telecommunications Engineering and Naval Architecture (DITEN), University of Genoa, where he is also leading the Telecommunication  ... 
doi:10.1109/jsyst.2015.2438639 fatcat:4ioq7wwpsbcvlhrpqs4z6kcat4

PODOS — The design and implementation of a performance oriented Linux cluster

Sudharshan Vazhkudai, Jeelani Syed, Tobin Maginnis
2002 Future generations computer systems  
This paper addresses the design and implementation of the various components of the PODOS system.  ...  These components are a Communication Manager (CM), a PODOS Distributed File System (PDFS), a Resource Manager (RM), and Global Interprocess Communication (GIPC).  ...  The use of state-full threads provides better performance and shorter messages over NFS that uses a state-less server.  ... 
doi:10.1016/s0167-739x(01)00055-3 fatcat:tuix7npoxzbkbnrs7prqlyin6u

Implementation Gifford Method For Digital Image Security

Fauduziduhu Laia, Erwin Panggabean
2020 Journal of Computer Networks, Architecture and High Performance Computing  
The processes performed by the Gifford method are the Output Function process, the 1-bit Sticky Shift Right process, the 1-bit Left Shift process, the XOR operation and the shift register operation to  ...  The Gifford method is a stream cipher, a symmetry encryption algorithm that transforms the data character by character. Gifford has 8 registers filled with key bits.  ...  To generate a random number, perform the merging operation (concatenate) between registers b0 and b2 registers and between registers and registers b4 b7.  ... 
doi:10.47709/cnapc.v2i2.418 fatcat:wm6hkc7xfjgddhorbl3rcxlrym

Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices [chapter]

Thomas Eisenbarth, Zheng Gong, Tim Güneysu, Stefan Heyse, Sebastiaan Indesteege, Stéphanie Kerckhof, François Koeune, Tomislav Nad, Thomas Plos, Francesco Regazzoni, François-Xavier Standaert, Loic van Oldeneel tot Oldenzeel
2012 Lecture Notes in Computer Science  
Second, we evaluate performance figures of our implementations with respect to different metrics, including energy-consumption measurements and show our improvements compared to existing implementations  ...  First, we provide implementations of 12 block ciphers on an ATMEL AVR ATtiny45 8-bit microcontroller, and make the corresponding source code available on a web page.  ...  In order to improve performance, the state is stored in 16 registers, while the key is stored in RAM. In addition, five temporary registers are used to implement the MixColumn step.  ... 
doi:10.1007/978-3-642-31410-0_11 fatcat:o4mzk643cvb6bevupyichljnm4

Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance

Shabana Aqueel, Kavita Khare
2011 International Journal of Computer Science & Information Technology (IJCSIT)  
The demand for faster and cheaper memories has been increasing by the day. Hence, these memory devices are rapidly developing to give high density and high memory bandwidths.  ...  This paper presents the overall architecture of the DDR3 Controller. Also the advantages of DDR3 over DDR2 and DDR are discussed.  ...  CONCLUSIONS The design study shows that high-performance and large lookup table circuits can be implemented using low-cost state-of-the-art FPGA and DDR3 technology.  ... 
doi:10.5121/ijcsit.2011.3408 fatcat:bqqc4ncqpjd2njcmy2ltwwz36u

Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices [chapter]

Josep Balasch, Bariş Ege, Thomas Eisenbarth, Benoit Gérard, Zheng Gong, Tim Güneysu, Stefan Heyse, Stéphanie Kerckhof, François Koeune, Thomas Plos, Thomas Pöppelmann, Francesco Regazzoni (+5 others)
2013 Lecture Notes in Computer Science  
All the implementations were carried out with the goal of minimizing the code size and memory utilization, and evaluated using a common interface.  ...  We implemented different algorithms on an ATMEL AVR ATtiny45 8-bit microcontroller, and provide their performance evaluation using different figures.  ...  To reduce code and clock cycles for such memory transfer operations, register name reassignment by circular pointer arithmetic is performed instead on the working registers residing in 256 bits of RAM.  ... 
doi:10.1007/978-3-642-37288-9_11 fatcat:asr3ev2z2rbc7gyxy2ipdfco5m

Implementation and performance aspects of Kahn process networks

Zeljko Vrba
2010 ACM SIGMultimedia Records  
We experimentally demonstrate that problems expressed in the Kahn model resemble very much their sequential implementations, yet perform much better than when expressed in the MapReduce model, which has  ...  In this thesis, we investigate the applicability of KPNs to implementing general-purpose parallel computations for multi-core machines.  ...  Closes the output channel files and outputs the KP's state to the Reduce stage. The send operation of step 1 shall yield (not block!)  ... 
doi:10.1145/1874413.1874418 fatcat:sm5wsqpyyfevtarf6336elhyny

Implementation and Performance Evaluation of a P2PSIP Distributed Proxy/Registrar

Jean-Francois Wauthy, Laurent Schumacher
2007 The 2007 International Conference on Next Generation Mobile Applications, Services and Technologies (NGMAST 2007)  
Three implementations, relying on OpenChord and Bamboo, are presented, and two of them are thoroughly tested in registration and call scenarios.  ...  In a distributed configuration with loadbalancing, this distributed Proxy/Registrar manages to handle 1,500+ REGISTER requests per second and 700+ call attempts per second.  ...  The BambooSipServlet showed poor performance (160 REGISTER requests per second) even decreasing (100 and 40 REGISTER requests per second) when adding nodes.  ... 
doi:10.1109/ngmast.2007.4343409 fatcat:f43iybrc7vfo3axx4cxpz4f4zq

SIP Signaling Implementations and Performance Enhancement over MANET: A Survey

Mazin Alshamrani, Haitham Cruickshank, Zhili Sun, Godwin Ansa, Feda Alshahwan
2016 International Journal of Advanced Computer Science and Applications  
However, the efficiency of these methods vary and depend on the identified performance metrics and the implementation platforms.  ...  This survey examines the implementation of the SIP signaling system for VoIP applications over MANET and highlights the available performance enhancement methods.  ...  After receiving the REGISTER message from the registration server, it extracts the user name, IP address, and port number then stores them in the location server [6] .  ... 
doi:10.14569/ijacsa.2016.070529 fatcat:74k3tmlur5dfnagntixuuav2gq
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