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Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop

Juan Pablo Martinez Brito, Sergio Bampi
2007 Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07  
In this paper, we explore the design of a Digital FM Receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL).  ...  A software-defined radio (SDR) is a wireless communication device in which all of the signal processing is implemented in software.  ...  The authors would like to thank the CAPES agency for PGMICRO support and the scholarship of CNPq/PNM Program.  ... 
doi:10.1145/1284480.1284522 dblp:conf/sbcci/BritoB07 fatcat:hzej2bjyijgohninqlmpezqhsm

Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

Juan Pablo Martinez Brito, Sergio Bampi
2008 Analog Integrated Circuits and Signal Processing  
In this paper, we explore the design of a digital FM receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL).  ...  In SDR devices, all of the signal processing is implemented in the digital domain, mainly on DSP blocks or by DSP software.  ...  Acknowledgments The authors would like to thank the CAPES agency for the support of the PGMICRO graduate Program and the scholarship of CNPq/PNM Program.  ... 
doi:10.1007/s10470-008-9184-7 fatcat:f4uwubdh75bblcmax4kkbfedyq

High-performance digital predistortion test platform development for wideband RF power amplifiers

Lei Guan, Ray Kearney, Chao Yu, Anding Zhu
2013 International journal of microwave and wireless technologies  
In this paper, a complete design procedure, together with robust system validation approaches, is presented for implementing a high performance re-configurable digital predistortion (DPD) test platform  ...  The experimental test was applied on a medium power Doherty amplifier, which was designed for 3G/4G wireless communication base stations.  ...  Because of its flexibility and excellent linearization performance, digital predistortion (DPD) has become one of the most preferred choices, and it also tends to be one of the essential units in wireless  ... 
doi:10.1017/s1759078713000184 fatcat:lt5wkgomprfvtnoeskofum5ve4

An Dynamic Energy Management On Fpga For Wireless Sensor Network

Alexandre Ingles Da Silva
2018 Zenodo  
In this project we built a low-power circuit applying the implementation of a technique to minimize the clocks number of the circuit and focusing on the dynamic power consumption of the architecture was  ...  Different analyses the consumption of a general architecture is shown and an operation mode acceptable to dynamic energy consumption of circuit to wireless sensor network on FPGA is achieved.  ...  The Nexys3 is a complete, readyto-use digital circuit development platform based on the Xilinx Spartan-6 LX16 FPGA.  ... 
doi:10.5281/zenodo.1436280 fatcat:z32tnkt5grdohfrt3vixjtqzre

Controlling and signal processing core for wireless implantable telemetry system

Naeeme Modir, Kyle Fricke, Zine-Eddine Abid, Robert Sobot
2016 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
Furthermore, the architecture of a typical wireless implantable telemetry system is briefly explained. In the end, FPGA-based prototyping for test and verification of an ASIC design is discussed.  ...  In [25] an FPGA-based prototype is used before the ASIC design to test and verify the performance of a proposed wireless endoscopy system.  ... 
doi:10.1109/icecs.2016.7841159 dblp:conf/icecsys/ModirFAS16 fatcat:7m25hqnbxjedtj4abj5zhfopsu

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

Indranil Hatai, Indrajit Chakrabarti
2011 International Journal of Reconfigurable Computing  
This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system.  ...  The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93  ...  Conclusions A new high-performance digital FM modulator and a digital phase-locked loop-based FM demodulator have been proposed in this paper.  ... 
doi:10.1155/2011/342532 fatcat:hybhzwxujjdqrgawwfa2qagwou

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  Since their introduction, FPGAs can be seen in more and more different fields of applications.  ...  The evaluation [5] concentrates on the architectural development and challenges of modern FPGAs. Nevertheless, it confirms the reasons for using FPGAs as a hardware platform given in this survey.  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Ali Kareem Nahar, Sabah A Gitaffa, Mohammed Moanes Ezzaldean, Hussain K Khleaf
2017 Review of Information Engineering and Applications  
With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding.  ...  Contribution/ Originality: This study contributes in the existing literature review for implementing MC-CDMA wireless communication system using Partial Reconfiguration (PR) that is a new technology in  ...  A Phase-Locked Loop (PLL) circuit is designed for carrier and symbol synchronization for recovery of data from the received signal. And different encoding scheme is also implemented.  ... 
doi:10.18488/journal.79.2017.41.1.19 fatcat:26rnarklqzajdj3hbepru44rxu

FPGA-Based Software-Defined Radio and Its Real-Time Implementation Using NI-USRP [chapter]

Nikhil Marriwala, Om. Prakash. Sahu, Anil Vohra
2017 Field - Programmable Gate Array  
In this chapter, we aim to provide a safe and private wireless transmission between two terminals using the SDR approach and verifying the results in real-world environment with the use of USRP.  ...  With the help of this design, we have been able to improve the stability of the system besides providing a reconfigurable and flexible architecture.  ...  The voltage-controlled oscillator (VCO) is controlled by the phase-locked loop (PLL) so that the device clocks and local oscillator (LO) can be frequency-locked to a reference signal. iii.  ... 
doi:10.5772/66272 fatcat:cqacvqlgwfh5nkz4xtdthkpnea

KUAR: A Flexible Software-Defined Radio Development Platform

G. J. Minden, J. B. Evans, L. Searl, D. DePardo, V. R. Petty, R. Rajbanshi, T. Newman, Q. Chen, F. Weidling, J. Guffey, D. Datla, B. Barker (+4 others)
2007 2007 2nd IEEE International Symposium on New Frontiers in Dynamic Spectrum Access Networks  
The KUAR hardware implementation and software architecture are discussed in detail. Radio configurations and applications are presented.  ...  The primary purpose of the KUAR is to enable advanced research in the areas of wireless radio networks, dynamic spectrum access, and cognitive radios.  ...  The RF front-end consists of multiple SMBUS 2 controlled components including phase-locked loops (PLL's), quadrature demodulator chips, analog to digital converters (ADC's), and digital to analog components  ... 
doi:10.1109/dyspan.2007.62 fatcat:hic6zbkzgjcdtpoad46fjwwr5q

A Rapid Prototyping Platform for Wireless Medium Access Control Protocols

Dean A. Armstrong, Murray W. Pearson
2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
The hardware architecture along with supporting firmware and software provides for a short design cycle in implementation of custom MAC protocols, and a large degree of flexibility in hardware/software  ...  Substantial research effort has been and continues to be invested into the study of existing protocols and the development of new and specialised ones, however researchers are restricted in their studies  ...  A digital Phase Locked Loop (PLL) tracks the synchronisation signal when present to alleviate long-term variations in timestamp clock frequency due to, for example, temperature differences between physically  ... 
doi:10.1109/asap.2007.4459297 dblp:conf/asap/ArmstrongP07 fatcat:u2ohxyh5y5c5bc63ttj3ngfu7u

Design of a high frequency FPGA acoustic modem for underwater communication

Nusrat Nowsheen, Craig Benson, Michael Frater
PLLs are being implemented more and more in the digital domain and all the components of the PLL need to be converted to discrete-time systems for implementing a digital PLL.  ...  The modem does all its processing in the digital domain and thus provides flexibility.  ...  This MUX is implemented in Altium using a VHDL code MUX3.Vhd.  ... 
doi:10.1109/oceanssyd.2010.5603819 fatcat:22rp3emfuvgbraushzyjwhaave

A Software-Defined Radio for Future Wireless Communication Systems at 60 GHz

Luis Duarte, Rodolfo Gomes, Carlos Ribeiro, Rafael F. S. Caldeirinha
2019 Electronics  
This paper reports on a complete end-to-end 5G mmWave testbed fully reconfigurable based on a FPGA architecture.  ...  In particular, the baseband unit design is based on a typical agile digital IF architecture, enabling on-the-fly modulations up to 256-QAM.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics8121490 fatcat:ca6lfxvj5ng7zgu4uvhh66azoe

Software Defined Radio: USRP N210 with GNU Radio

, professors as well as students working in the area of signal processing and wireless communication.  ...  Furthermore, this paper presents the implementation of basic analog/digital modulation techniques, and recent research works carried out by using SDR.  ...  ., designed a low cost and low complexity digital transceiver employing RTL-SDR and Stefan et al., implemented modulator/demodulator arts of a digital video broadcasting (DVB) -T2 transceiver.  ... 
doi:10.35940/ijitee.e2736.039520 fatcat:55pf27un5jaexjsxwvqcxl3t7m

Evaluation Of Sdr Using Open Source Technology

Pravesh Patil, Leena Govekar, Y. S. Rao
2017 Zenodo  
This article reviews investigation on the current equipment stage for SDR. It highlights the interfacing of AD-FMCommS4 with ZedBoard.  ...  Considering the wide demand of wireless communication, the paper aims to propose a flexible platform for software-defined radio, which will be able to meet the wide spectrum from 70 MHz to 6 GHz.  ...  It uses a reprogrammable ability of Field Programming Gate Array (FPGA) or digital signal processor to build an open architecture with the software implementation of radio frequencies such as modulation  ... 
doi:10.5281/zenodo.1130794 fatcat:jxje6lklrnflxhksu6xvsec24i
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