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Exploring the design space for a shared-cache multiprocessor

B. A. Nayfeh, K. Olukotun
1994 SIGARCH Computer Architecture News  
We study the performance of a cluster-based multiprocessor architecture in which processors within a cluster are tightly coupled via a shared cluster cache for various processor-cache configurations.  ...  In this paper we investigate the architecture and partitioning of resources between processors and cache memory for single chip and MCM-based multiprocessors.  ...  Acknowledgments We would like to thank Kun-Yung Chang for his help in developing the implementation and cost models for the shared cluster caches and Bharadwaj Amurtur for his SRAM design parameters.  ... 
doi:10.1145/192007.192026 fatcat:ntywckvlzfczzmndlob5wd57si

Cache-coherent distributed shared memory: perspectives on its development and future challenges

J. Hennessy, M. Heinrich, A. Gupta
1999 Proceedings of the IEEE  
Cache coherence allows such architectures to use caching to take advantage of locality in applications without changing the programmer's model of memory.  ...  We review the key developments that led to the creation of cache-coherent distributed shared memory and describe the Stanford DASH Multiprocessor, the first working implementation of hardware-supported  ...  The snoopy cache coherence schemes and the bus-based interconnect used in small-scale shared memory multiprocessors work well together for three reasons.  ... 
doi:10.1109/5.747863 fatcat:koqfmkqdibaylcxfiheb33bwly

Hierarchical cache/bus architecture for shared memory multiprocessors

A. W. Wilson
1987 Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87  
A new, large scale multiprocessor architecture is presented in this paper. The architecture consists of hierarchies of shared buses and caches.  ...  Extended versions of shared bus multicache coherency protocols are used to maintain coherency among all caches in the system.  ...  Thus multi-cache coherency algorithms should concentrate on minimizing impact in the non-shared case, rather than the actively shared one.  ... 
doi:10.1145/30350.30378 dblp:conf/isca/Wilson87 fatcat:yyaqljc45fe7ncgymfmmjikf2e

Design of a scalable multiprocessor architecture and its simulation

Der-Lin Pean, Chao-Chin Wu, Huey-Ting Chua, Cheng Chen
2001 Journal of Systems and Software  
Performance enhancement and system scalability are two of the most important issues in the design of multiprocessor systems.  ...  Our cluster-based multiprocessor architecture also scales more readily than the current general, or cluster-based, multiprocessor environments. Ó  ...  Acknowledgements This research was supported by the National Science Council of the Republic of China under contract number NSC 87-2213-E009-049.  ... 
doi:10.1016/s0164-1212(01)00034-6 fatcat:ix6rj2i3grfbfgk3ha23bd4udq

Shared Memory Multiprocessors [chapter]

2004 Parallel Computing on Heterogeneous Networks  
Until recently, this was the dominating architecture for small-scale multiprocessors.  ...  With the exception of clustered multiprocessors, all of the above architectures provide all cores in the system with access to a shared physical address space.  ... 
doi:10.1002/0471654167.ch3 fatcat:dvaj7kmetfgr7bkmdrmvzljwda

MGS

Donald Yeung, John Kubiatowicz, Anant Agarwal
1996 SIGARCH Computer Architecture News  
This paper explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems.  ...  We call these systems Distributed Scalable Shared-memory Multiprocessors (DSSMPs).  ...  drafts of this paper.  ... 
doi:10.1145/232974.232980 fatcat:lxsfs2y74ndhfjzqnzrzkpga64

MGS

Donald Yeung, John Kubiatowicz, Anant Agarwal
1996 Proceedings of the 23rd annual international symposium on Computer architecture - ISCA '96  
This paper explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems.  ...  We call these systems Distributed Scalable Shared-memory Multiprocessors (DSSMPs).  ...  drafts of this paper.  ... 
doi:10.1145/232973.232980 dblp:conf/isca/YeungKA96 fatcat:nprbszfczrhnzosqc2fb3cktom

The scalability of multigrain systems

Donald Yeung
1999 Proceedings of the 13th international conference on Supercomputing - ICS '99  
Researchers have recently proposed coupling small-to mediumscale multiprocessors to build large-scale shared memory machines, known as multigrain shared memory systems.  ...  Using the model, the paper conducts an in-depth study of multigrain system scalability.  ...  Each type of scaling has a different impact on machine behavior. Scaling node size increases the amount of shared memory hardware in the system.  ... 
doi:10.1145/305138.305203 dblp:conf/ics/Yeung99 fatcat:eaao3nq4cfbsdmxy5gnrhyqr5u

The benefits of clustering in shared address space multiprocessors

Andrew Erlichson, Basem A. Nayfeh, Jaswinder P. Singh, Kunle Olukotun
1995 Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '95  
Clustering processors together at a level of the memory hierarchy in shared address space multiprocessors appears to be an attractive technique from several standpoints: Resources are shared, packaging  ...  We investigate the performance benefits that can be obtained by clustering on a range of important scientific and engineering applications in moderate to large scale cache coherent machines with small  ...  Kunle Olukotun is supported partially by a grant from the Powell Foundation.  ... 
doi:10.1145/224170.224397 dblp:conf/sc/ErlichsonNSO95 fatcat:2f3tee22ofduzob4d3jcfqydau

A two-level directory architecture for highly scalable cc-NUMA multiprocessors

M.E. Acacio, J. Gonzalez, J.M. Garcia, J. Duato
2005 IEEE Transactions on Parallel and Distributed Systems  
One important issue the designer of a scalable shared-memory multiprocessor must deal with is the amount of extra memory required to store the directory information.  ...  It is desirable that the directory memory overhead be kept as low as possible, and that it scales very slowly with the size of the machine.  ...  This work has been supported in part by the Spanish Ministry of Ciencia y Tecnología and the European Union (Feder Funds) under grant TIC2003-08154-C06-03.  ... 
doi:10.1109/tpds.2005.4 fatcat:3hcdkjqiwjh55in3d4uph6gdfq

Multigrain shared memory

Donald Yeung, John Kubiatowicz, Anant Agarwal
2000 ACM Transactions on Computer Systems  
This paper explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems.  ...  Multigrain shared memory enables the collaboration of hardware and software shared memory, thus synthesizing a single transparent shared memory address space across a cluster of multiprocessors.  ...  \Neighborhoods" of tight coupling are formed using cache-coherent shared memory within small-to medium-scale multiprocessor nodes.  ... 
doi:10.1145/350853.350871 fatcat:s32qyjg7wra7jc6iho426iczra

Toward Large-Scale Shared Memory Multiprocessing [chapter]

John K. Bennett, John B. Carter, Willy Zwaenepoel
1992 Scalable Shared Memory Multiprocessors  
Willow i s distinguished from other shared memory multiprocessors by a l a yered memory organization that signi cantly reduces the impact of inclusion on the cache hierarchy and that exploits locality  ...  These processors are arranged in cluster fashion, with a m ulti-level cache, I/O, synchronization, and memory hierarchy.  ...  ACKNOWLEDGEMENTS Other members of the Computer Systems Laboratory have participated in the development o f m a n y of the ideas that we h a ve presented.  ... 
doi:10.1007/978-1-4615-3604-8_15 fatcat:k7qiuyjnbzc5bkx4eenkrzmvxq

Thread clustering

David Tam, Reza Azimi, Michael Stumm
2007 Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007 - EuroSys '07  
As a result, even low-end computing systems and game consoles have become shared memory multiprocessors with L1 and L2 cache sharing within a chip.  ...  Mid-and large-scale systems will have multiple processing chips and hence consist of an SMP-CMP-SMT configuration with non-uniform data sharing overheads.  ...  ACKNOWLEDGEMENTS We would like to thank a number of individuals and organizations for their support. Cristiana Amza and Gokul Soundararajan provided the RUBiS database workload.  ... 
doi:10.1145/1272996.1273004 dblp:conf/eurosys/TamAS07 fatcat:lcveqmymibflbj2fryg46ygx2i

Thread clustering

David Tam, Reza Azimi, Michael Stumm
2007 ACM SIGOPS Operating Systems Review  
As a result, even low-end computing systems and game consoles have become shared memory multiprocessors with L1 and L2 cache sharing within a chip.  ...  Mid-and large-scale systems will have multiple processing chips and hence consist of an SMP-CMP-SMT configuration with non-uniform data sharing overheads.  ...  ACKNOWLEDGEMENTS We would like to thank a number of individuals and organizations for their support. Cristiana Amza and Gokul Soundararajan provided the RUBiS database workload.  ... 
doi:10.1145/1272998.1273004 fatcat:5oykqfybirdknl75tpozofotxq

Scalable and Flexible heterogeneous multi-core system

Rashmi, Dr. Dinesh
2012 International Journal of Advanced Computer Science and Applications  
Use of high memory-level parallelism (MLP) reduces the memory wall. Micro architecture contains a set of small and fast cache processors which execute high locality code.  ...  A network of small in-order memory engines use low locality code to improve performance by using instruction level parallelism (ILP).  ...  able to make the most of the shared cache for sharing.  ... 
doi:10.14569/ijacsa.2012.031227 fatcat:m4vqub3x2fc7jlwm7dsb47ngzy
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