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Friends, not foes

Ali Munir, Ghufran Baig, Syed M. Irteza, Ihsan A. Qazi, Alex X. Liu, Fahad R. Dogar
2014 Proceedings of the 2014 ACM conference on SIGCOMM - SIGCOMM '14  
PASE is deployment friendly: it does not require any changes to the network fabric; yet, its performance is comparable to, or better than, the state-of-the-art protocols that require changes to network  ...  Our results show that PASE performs well for a wide range of application workloads and network settings.  ...  Acknowledgements: We thank our shepherd, Nandita Dukkipati, and the SIGCOMM reviewers for their feedback. We also thank Thomas Karagiannis and Zafar Ayyub Qazi for their useful comments.  ... 
doi:10.1145/2619239.2626305 dblp:conf/sigcomm/MunirBIQLD14 fatcat:aly4gonub5dmno26dep5npx2gy

Design and evaluation of a switch cache architecture for CC-NUMA multiprocessors

R.R. Iyer, L.N. Bhuyan
2000 IEEE transactions on computers  
We explore the design space of switch caches by modeling CAESAR in a detailed execution driven simulator and analyze the performance benefits.  ...  Our results show that the CAESAR switch cache is capable of improving the performance of CC-NUMA multiprocessors by up to 45 percent reduction in remote memory accesses for some applications.  ...  However, the use of switch caches still has significant impact on application performance.  ... 
doi:10.1109/12.868025 fatcat:t77mkwpnofhphhsoxd4ozuw6uy

The NoX router

Mitchell Hayenga, Mikko Lipasti
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
This paper proposes the use of a novel coding-based crossbar architecture to perform packet arbitration in parallel with switch traversal.  ...  The use of a lightweight exclusive-OR (XOR) coding scheme enables the productive transmission of packets, without waiting for arbitration, even under contention.  ...  This has the impact of allowing a packet to progress through the switch during the current cycle, while using the arbitration logic to schedule the packet to be transmitted on the next clock cycle.  ... 
doi:10.1145/2155620.2155626 dblp:conf/micro/HayengaL11 fatcat:f4eiqclvrfc6jes3u4rn6z2sq4

Network-on-chip with an arbitration control for balancing throughputs in multiprocessor applications

Faizal Arya Samman
2014 2014 Makassar International Conference on Electrical Engineering and Informatics (MICEEI)  
This paper presents an arbitration mechanism to balance bandwidth consumption or data throughputs between packets in a network-on-chip (NoC) with ID-based wormhole cut-through switching method.  ...  When data traffic flowing through a network communication link is high, the bandwidth space of the link, which is comsumed by a message or a data stream, could be affected by the distance between the source  ...  EXPERIMENTAL RESULTS In order to see directly the impact of the proposed arbitration method on the performance characteristics of NoC, an experimental simulation will be presented in this paper by using  ... 
doi:10.1109/miceei.2014.7067318 fatcat:4ju4otoxcfeerjwb3rwtej5byq

Evaluation of alternative arbitration policies fo myrinet switches

P.J. Garcia, M.D. Mora, F.J. Alfaro, J.L. Sanchez, J. Flich
2002 Proceedings 16th International Parallel and Distributed Processing Symposium  
Interconnection networks consist of a set of switches interconnected by point-to-point links, and hosts linked to those switches through a network interface card.  ...  One of these techniques is the use of crossbar chips as the main component of switches, allowing to connect the input channel of any of their ports to the output channel of any of their ports for forwarding  ...  As future work we plan to study the effect of the policies with real applications with an execution-driven simulator as well as the impact on different proposed routing algorithms.  ... 
doi:10.1109/ipdps.2002.1016560 dblp:conf/ipps/GarciaMASF02 fatcat:f7xhhinm7zbf3atmaupkyxztoe

Layered switching for networks on chip

Zhonghai Lu, Ming Liu, Axel Jantsch
2007 Proceedings - Design Automation Conference  
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching.  ...  To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture.  ...  The first level of arbitration is performed on the lanes sharing the same input port to the crossbar. The second level of arbitration is for the crossbar traversal to output links.  ... 
doi:10.1145/1278480.1278511 dblp:conf/dac/LuLJ07 fatcat:ytgfg2kmazggljl7lyzoatyljy

Layered Switching for Networks on Chip

Zhonghai Lu, Ming Liu, Axel Jantsch
2007 Proceedings - Design Automation Conference  
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching.  ...  To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture.  ...  The first level of arbitration is performed on the lanes sharing the same input port to the crossbar. The second level of arbitration is for the crossbar traversal to output links.  ... 
doi:10.1109/dac.2007.375137 fatcat:kmh6jblhmzdlrnjbhfyq2kcfge

The role of optics in future high radix switch design

Nathan Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
2011 Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11  
We compare the power and performance of switches of radix 64, 100, and 144 in the 45, 32, and 22 nm technology steps.  ...  Overall, the adoption of photonic I/O allows 100,000 port networks to be constructed with less than one third the power of equivalent all-electronic networks.  ...  The optical arbitration round trip time is also less than eight clocks and the arbitration power has a negligible impact on total switch power.  ... 
doi:10.1145/2000064.2000116 dblp:conf/isca/BinkertDJMMSA11 fatcat:dwnygpxa3zgi3l6sp36hcks5ce

The role of optics in future high radix switch design

Nathan Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
2011 SIGARCH Computer Architecture News  
We compare the power and performance of switches of radix 64, 100, and 144 in the 45, 32, and 22 nm technology steps.  ...  Overall, the adoption of photonic I/O allows 100,000 port networks to be constructed with less than one third the power of equivalent all-electronic networks.  ...  The optical arbitration round trip time is also less than eight clocks and the arbitration power has a negligible impact on total switch power.  ... 
doi:10.1145/2024723.2000116 fatcat:ysgjvbnbfzdmhllqvih5d3bvje

IMPLEMENTATION OF VIRTUAL CHANNEL ROUTER WITH VA AND SA ARBITRATION UNIT USING VHDL

Minakshi M Wanjari, Pankaj Agrawal, Ravi V Kshirsagar
2019 International Journal of Engineering Applied Sciences and Technology  
Router control logic consists of virtual channel arbitration unit and switch allocation unit. The source code is written in VHDL.  ...  Router is the backbone of NoC which performs the essential task of guiding and coordinating the data flow and determines the performance to a large extend.  ...  VA is also a "per-packet" operation; it is only performed on header flits. 3) Switch Allocation (SA) Unit: The Switch Allocation unit arbitrates between all VCs requesting access to the crossbar and  ... 
doi:10.33564/ijeast.2019.v04i05.022 fatcat:6ut7xizue5dcld746odjwabqdm

OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip

Ramon Fernandes, Lucas Brahm, Thais Webber, Rodrigo Cataldo, Leticia B. Poehls, Cesar Marcon
2015 2015 28th International Conference on VLSI Design  
The overall system-on-chip performance depends on the network architecture, whose communication latency significantly impacts on the application performance.  ...  One alternative to achieve such goals is to implement efficient router architectures capable of fast packet switching and routing for parallel and scalable Networks-on-Chip (NoCs).  ...  Independent on the NoC layer, every router has the same architecture and size, and independent on link connection (i.e. horizontal or vertical), flits are transmitted with the same quantity of clock cycles  ... 
doi:10.1109/vlsid.2015.23 dblp:conf/vlsid/FernandesBWCPM15 fatcat:qxxpuut7azh55bqgr4j3vihyoq

pp-mess-sim: a flexible and extensible simulator for evaluating multicomputer networks

J. Rexford, Wu-Chang Feng, J. Dolter, K.G. Shin
1997 IEEE Transactions on Parallel and Distributed Systems  
, traffic patterns, and performance metrics with collections of packets, instead of the underlying router model.  ...  The simulator provides a toolbox of various network topologies, communication workloads, routing-switching algorithms, and router models.  ...  Any opinions, findings, and conclusions or recommendations expressed in this paper are those of the authors and do not necessarily reflect the view of the National Science Foundation.  ... 
doi:10.1109/71.569653 fatcat:u47by6qsbbhbnbfa2vs7xd5agy

QNoC asynchronous router

Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
2009 Integration  
Analytical expressions for a generic NoC router performance, area and power are derived, showing linear dependence on the number of buffers and flit width.  ...  The router employs fast arbitration schemes to minimize latency.  ...  Acknowledgement This research was funded in part by Freescale Semiconductor and Semiconductor Research Corporation (1204.001), Israel Ministry of Industry and Trade (Short Range Radio Consortium) and by  ... 
doi:10.1016/j.vlsi.2008.03.001 fatcat:nbby3m7tfbcm7ft3nvyxfewvce

FLOWS: performance guarantees in best effort delivery systems

D. Comer, R. Yavatkar
1989 IEEE INFOCOM '89, Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies  
This paper describes the concept of flows in detail and presents algorithms that implement flows in a high speed packet switched network under development at Purdue University.  ...  This paper describes the concept of flows in detail and presents algorithms that implement flows in a high speed packet switched network under development at Purdue University.  ...  A link level flow arbitrator guarantees, barring a flow failure, to deliver packets in the flow with performance bounds specified at the time of flow creation.  ... 
doi:10.1109/infcom.1989.101442 dblp:conf/infocom/ComerY89 fatcat:grlokeabsvdole75hwy6puigia

Swizzle-Switch Networks for Many-Core Systems

Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David Blaauw, Trevor Mudge
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Compared to a conventional Mesh, the Flattened Butterfly provides a 15% performance improvement with a 2.5 reduction in the standard deviation of on-chip access times.  ...  Finally, this paper details a 3-D integrated version of the Swizzle-Switch Network, showing up to a 30% gain in performance over the 2-D Swizzle-Switch Network for benchmarks sensitive to interconnect  ...  stages. 3) Out-of-Order Cores: We demonsrate the performance impact of using out-of-order (O3) cores on a 64-core system in Fig. 17 .  ... 
doi:10.1109/jetcas.2012.2193936 fatcat:mt7funcufbfwdo2ik4bsamcaki
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