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Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies

Yao HU, Michihiro KOIBUCHI
2020 IEICE transactions on information and systems  
We make a comparative study to analyze the impact of application mapping performance on non-random and random network topologies.  ...  Random network topologies can be built for any pair of the number of nodes and degree.  ...  Figure 1 depicts an example of application mapping over a non-random (2-D mesh) network topology and a random network topology respectively, which have the same degree of four.  ... 
doi:10.1587/transinf.2020pap0006 fatcat:t5ept75md5d3vibfktghqrtybe

Improved MDS-based algorithm for nodes localization in wireless sensor networks

Biljana Risteska Stojkoska, Vesna Kirandziska
2013 Eurocon 2013  
With the recent development of technology, wireless sensor networks (WSN) are becoming an important part of many applications.  ...  Using extensive simulations we investigated in details our approach regarding different network topologies, various network parameters and performance issues.  ...  MAP and IMDS on random topology (100 nodes randomly deployed) without range error random topology (100 nodes randomly deployed) with range error 5% of R , IMDS performs smaller MAP for both random and  ... 
doi:10.1109/eurocon.2013.6625044 dblp:conf/eurocon/StojkoskaK13 fatcat:5isi2wf5ffbwpglmyxfzpv7tcy

Profiling and mapping of parallel workloads on network processors

Ning Weng, Tilman Wolf
2005 Proceedings of the 2005 ACM symposium on Applied computing - SAC '05  
An architecture independent representation of the runtime behavior of the application is used to map and schedule different processing steps to the underlying hardware.  ...  To meet the performance demands of increasing link speeds and more complex network applications, network processors are implemented with several dozens of processor cores and execute multiple packet processing  ...  Acknowledgements The authors would like to thank Ramaswamy Ramaswamy for providing the run-time instruction traces that were used for the ADAG generation.  ... 
doi:10.1145/1066677.1066879 dblp:conf/sac/WengW05 fatcat:r2xa4y77l5erninwi247dhmxuy

Avoiding hot-spots on two-level direct networks

Abhinav Bhatele, Nikhil Jain, William D. Gropp, Laxmikant V. Kale
2011 Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis on - SC '11  
Routing and mapping choices can impact the communication performance of parallel applications running on a machine with a two-level direct topology.  ...  IBM's PERCS topology and the dragonfly network discussed in the DARPA exascale hardware study are examples of this design.  ...  Runs for this paper were done on Blue Print and Ember, resources at NCSA. The authors would like to thank Ryan Mokos for building the Blue Waters network simulation model used in this paper.  ... 
doi:10.1145/2063384.2063486 dblp:conf/sc/BhateleJGK11 fatcat:m5fwcxh5hbe2jirouvmkwwj6zy

Power Aware IP Block Mapping Schemes for Interconnect Networks

Xinyu Wang, Zhigang Yu
2017 International Journal of Control and Automation  
This paper investigates the influence of IP block mapping on power, and finds that power-efficient mapping is crucial to the overall system.  ...  Experimental results show that the proposed methods are competitive, and outperform random mapping scheme in solving the problem.  ...  Impact of Topology Selection For comparison purposes, we also implement random mapping (RM) by randomly mapping IP blocks onto routers in different topologies.  ... 
doi:10.14257/ijca.2017.10.3.18 fatcat:wycxwd57urbundikrt2jchikt4

Optimization-based mapping framework for parallel applications

Jose A. Pascual, Jose Miguel-Alonso, Jose A. Lozano
2011 Journal of Parallel and Distributed Computing  
The way tasks are mapped onto processors (network nodes) has a remarkable impact on the performance of parallel applications, and on the performance of the parallel system as a whole [1].  ...  The optimal mapping of tasks of a parallel program onto nodes of a parallel computing system has a remarkable impact on application performance.  ...  The behaviour of a particular mapping, measured in terms of application speed, depends on many aspects: physical topology of the network, partitioning schema, virtual topology of the application, and other  ... 
doi:10.1016/j.jpdc.2011.06.005 fatcat:selwofdlu5ebdftbmgsxadiarm

An Evaluation of Network Architectures for Next Generation Supercomputers

Dong Chen, Philip Heidelberger, Craig Stunkel, Yutaka Sugawara, Cyriel Minkenberg, Bogdan Prisacari, German Rodriguez
2016 2016 7th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS)  
Through a combination of analysis and simulation on selected supercomputer workloads, we compare these networks according to desirable network properties such as robust performance, low cost, and partitionability  ...  We survey network topologies, in particular networks with full all-to-all bandwidth scaling.  ...  This work was supported and partially funded by Lawrence Berkeley National Laboratory (LBNL), on behalf of the US Department of Energy, under LBNL subcontract number 7078416.  ... 
doi:10.1109/pmbs.2016.007 dblp:conf/sc/ChenHSSMPR16 fatcat:qyfqu7faurfjnmunuresfhto44

Bio-instantiated recurrent neural networks: Integrating neurobiology-based network topology in artificial networks

Alexandros Goulas, Fabrizio Damicelli, Claus C. Hilgetag
2021 Neural Networks  
Biological neuronal networks (BNNs) are a source of inspiration and analogy making for researchers that focus on artificial neuronal networks (ANNs).  ...  We investigate the performance of bio-instantiated RNNs in terms of: (i) the prediction performance itself, that is, the capacity of the network to minimize the cost function at hand in test data, and  ...  Binary and weighted topology Innate cognition and fast learning pertaining to animals may be based on the non-random network topology of the brain Zador (2019).  ... 
doi:10.1016/j.neunet.2021.07.011 pmid:34391175 fatcat:yvckojv6qvha3ehwcgvbinke7m

On the Evolution of Complex Network Topology Under Network Churn [chapter]

Vasileios Karyotis, Eleni Stai, Symeon Papavassiliou
2016 Lecture Notes in Computer Science  
The impact of network churn on network structure, management and application services has been more or less neglected in the literature.  ...  For random edge churn, the most important observations are that it has almost no impact on RG topologies, lesser (and small) impact on SF and noteworthy impact on SW (which move closer to RG topologies  ... 
doi:10.1007/978-3-319-33936-8_18 fatcat:7ng7kdhuu5fslmpmp4dfmpvypm

Bio-instantiated recurrent neural networks [article]

Alexandros Goulas, Fabrizio Damicelli, Claus C Hilgetag
2021 bioRxiv   pre-print
We highlight what strategies can be used to construct RNNs with the network topology found in nature, without sacrificing prediction capacity and speed of training.  ...  Biological neuronal networks (BNNs) constitute a niche for inspiration and analogy making for researchers that focus on artificial neuronal networks (ANNs).  ...  Deutsche Forschungsgemeinschaft (SPP 2041 2888/2-2) FD: Deutscher Akademischer Austausch Dienst (DAAD), CCH: Deutsche Forschungsgemeinschaft (SFB 936/A1; TRR 169/A2; SPP 2041/HI 1286/7-1, HI 1286/6-1), the  ... 
doi:10.1101/2021.01.22.427744 fatcat:uiydrmys5zaq7d4fqa3jexsnaa

Layout-conscious random topologies for HPC off-chip interconnects

M. Koibuchi, I. Fujiwara, H. Matsutani, H. Casanova
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large.  ...  We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.  ...  ACKNOWLEDGMENTS This work was partially supported by JST CREST and by NSF Award CNS-0855245.  ... 
doi:10.1109/hpca.2013.6522343 dblp:conf/hpca/KoibuchiFMC13 fatcat:lkozfi554fffrfvxfgomoj2pc4

Robust PRNG based on homogeneously distributed chaotic dynamics

Oleg Garasym, René Lozi, Ina Taralova
2016 Journal of Physics, Conference Series  
Exploring several topologies of network of 1-D coupled chaotic mapping, we focus first on two dimensional networks.  ...  The primary idea of the novel maps has been based on an original coupling of the tent and logistic maps to achieve excellent random properties and homogeneous /uniform/ density in the phase plane, thus  ...  Hence, if we use T L µ to make impact on the dynamics of simple maps, then excellent effect on chaoticity and randomness could be achieved.  ... 
doi:10.1088/1742-6596/692/1/012011 fatcat:hzol5u5cf5frjma4usojgus344

Benefits of Topology Aware Mapping for Mesh Interconnects

Abhinav Bhatelé, Laxmikant V. Kalé
2008 Parallel Processing Letters  
It shows that even for simple benchmarks, topology-aware mapping can have a significant impact on performance.  ...  Automated topology-aware mapping by the runtime using similar ideas can relieve the application writer from this burden and result in better performance.  ...  This research also used running time on Blue Gene/P of the Argonne Leadership Computing Facility at Argonne National Laboratory, which is supported by the Office of Science of the U.S.  ... 
doi:10.1142/s0129626408003569 fatcat:xanlzwzqvngrxaj6bnptsvlmci

Augmenting low-latency HPC network with free-space optical links

Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
The network topology, which connects switches in cabinets on a machine room floor, is typically defined once and for all at system deployment time.  ...  We then demonstrate that the use of FSO links improves the embedding/partitioning capabilities of a wired topology.  ...  ACKNOWLEDGMENTS We give a special thanks to Shinichi Ishida, Cyber-Koubou LLC, Japan, for making the FSO terminal prototype; and to Yoshinori Arimoto, National Institute of Information and Communications  ... 
doi:10.1109/hpca.2015.7056049 dblp:conf/hpca/FujiwaraKOMC15 fatcat:cyjmby6wg5frbdlgcinueu5doi

A case for random shortcut topologies for HPC interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large.  ...  Using graph analysis we find that these topologies, when compared to non-random topologies of the same degree, lead to drastically reduced diameter and average shortest path length.  ...  ACKNOWLEDGMENTS This work was partially supported by JST CREST and by NSF Award CNS-0855245.  ... 
doi:10.1109/isca.2012.6237016 dblp:conf/isca/KoibuchiMAHC12 fatcat:gn5k7edymbehde2abrlnwmxcqa
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