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The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization

Eduardo Quinones, Sara Royuela, Claudio Scordino, Paolo Gai, Luis Miguel Pinho, Luis Nogueira, Jan Rollo, Tommaso Cucinotta, Alessandro Biondi, Arne Hamann, Dirk Ziegenbein, Hadi Saoud (+5 others)
2020 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)  
These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance  ...  Index Terms-parallel programming models, parallel and heterogeneous embedded processor architectures, model-driven approaches, safety-critical embedded systems  ...  It will incorporate multiple operating systems supporting a variety of architectures and accelerators, as well as a safe and secure real-time hypervisor capable of running on the target architectures and  ... 
doi:10.1109/isorc49007.2020.00042 dblp:conf/isorc/QuinonesRSGPNRC20 fatcat:4dse2jqgmvcbjbch4pfomq4kyi

Programming MPSoC platforms: Road works ahead!

R. Leupers, A. Vajda, M. Bekooij, Soonhoi Ha, R. Domer, A. Nohl
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
Efficient utilization of the MPSoC HW resources demands for radically new models and corresponding SW development tools, capable of exploiting the available parallelism and guaranteeing bug-free parallel  ...  Even more important from a SW developer´s viewpoint, at the same time the classical sequential von Neumann programming model needs to be overcome.  ...  In section III, different models for scheduling real-time tasks are discussed. Section IV describes MAPS, a prototype tool for semi-automatic code parallelization and task-to-processor mapping.  ... 
doi:10.1109/date.2009.5090917 fatcat:dz4ubgggofc3dnfqlnyknucgsa

Execution-driven simulators for parallel systems design

Anand Sivasubramaniam
1997 Proceedings of the 29th conference on Winter simulation - WSC '97  
Evaluating, analyzing and predicting the performance of a parallel system is challenging due to the complex inter-play between the application characteristics and architectural features.  ...  At the heart of this framework is an execution-driven simulation testbed called SPASM which uses a suite of real applications as the workload.  ...  ACKNOWLEDGMENTS This research is supported in part by a NSF Career Award MIP-9701475 and equipment grants from NSF and IBM.  ... 
doi:10.1145/268437.268735 fatcat:7a5agovbwrhi5oyinjytbgaqya

Co-Design of Multicore Hardware and Multithreaded Software for Thread Performance Assessment on an FPGA

George K. Adam
2022 Computers  
The increase in cores and threads, however, raises further issues in the efficiency achieved in terms of speedup and parallelization, particularly for the real-time requirements of Internet of things (  ...  This research investigates the efficiency of a 32-core field-programmable gate array (FPGA) architecture, with memory management unit (MMU) and real-time operating system (OS) support, to exploit the thread  ...  PThreads is an execution model that exists independently from a language and a parallel execution model. POSIX Threads is an API defined by the standard IEEE POSIX.1c.  ... 
doi:10.3390/computers11050076 fatcat:kyuy3opsg5h2fputitwzedltim


Michel Barreteau, Juliette Mattioli, Thierry Grandpierre, Christophe Lavarenne, Yves Sorel, Philippe Bonnot, Philippe Kajfasz
2000 Proceedings of the international conference on Compilers, architectures, and synthesis for embedded systems - CASES '00  
Increasing of computation needs and improving of processor integration make the mapping of embedded real-time applications more and more expensive.  ...  PROMPT [1] provides a new approach which relies on the co-operation of two technologies whose main strength consists in simultaneously taking into account regular and irregular aspects of telecom applications  ...  SynDEx [4] (INRIA) is a system-level CAD for rapid prototyping and optimizing the implementation of real-time embedded applications on heterogeneous and homogeneous multiprocessor architectures.  ... 
doi:10.1145/354880.354887 dblp:conf/cases/BarreteauMGLSBK00 fatcat:oujnkk2tercbbnxupqclbtkofi

JEOPARD -- Java Environment for Parallel Real-Time Development

Fridtjof Siebert
2009 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing  
This paper gives an overview of the JEOPARD project and focuses on key technical issues such as real-time scheduling and realtime garbage collection on multi-core systems.  ...  Multicore systems have become standard for desktop computers today. Current operating systems and software development tools provide straightforward means to use the additional computing power.  ...  Acknowledgements This work was partially funded by the European Commission's 7th framework program's JEOPARD project, number 216682.  ... 
doi:10.1109/isorc.2009.48 dblp:conf/isorc/Siebert09 fatcat:fmm3wrfbgnbcrj3kejtpn67clm

Rsim: simulating shared-memory multiprocessors with ILP processors

C.J. Hughes, V.S. Pai, P. Ranganathan, S.V. Adve
2002 Computer  
Rsim is a publicly available architecture simulator for shared-memory systems built from processors that aggressively exploit instruction-level parallelism.  ...  Modeling ILP features in a multiprocessor is particularly important for applications that exhibit parallelism among read misses.  ...  Acknowledgments The Rsim project began while the authors were at Rice University. It  ... 
doi:10.1109/2.982915 fatcat:llmomku5z5cffaf22hadpdvlhy


Fridtjof Siebert
2008 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems - JTRES '08  
This paper gives an overview of the JEOPARD project and focuses on key technical issues such as real-time scheduling and realtime garbage collection on multi-core systems.  ...  Multicore systems have become standard for desktop computers today. Current operating systems and software development tools provide straightforward means to use the additional computing power.  ...  Acknowledgements This work was partially funded by the European Commission's 7th framework program's JEOPARD project, number 216682.  ... 
doi:10.1145/1434790.1434804 dblp:conf/jtres/Siebert08 fatcat:uoiptzaodfdfneyb3ipxnqla5u

Model-integrated program synthesis environment for parallel/real-time image processing

Michael S. Moore, Janos Sztipanovitz, Gabor Karsai, James A. Nichols, Hongchi Shi, Patrick C. Coffield
1997 Parallel and Distributed Methods for Image Processing  
MIRTIS employs the Multigraph Architecture MGA, a framework and set of tools for building MIPS systems, to generate parallel real-time image processing software which runs under the control of a parallel  ...  The complex details inherent to parallel and real-time software development become transparent to the programmer, enabling the cost-e ective exploitation of parallel hardware for building more exible and  ...  ACKNOWLEDGEMENTS This work was partially supported by the AFOSR AFMC, US Air Force, contract number F49620-94-C-0076.  ... 
doi:10.1117/12.279633 fatcat:k3owikur2ffjpfigg7adiq2nim

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Javad Zarrin, Rui L. Aguiar, João Paulo Barraca
2017 Simulation modelling practice and theory  
In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques.  ...  The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development  ...  For example, timing models can be multiple orders of magnitude slower than real time.  ... 
doi:10.1016/j.simpat.2016.12.014 fatcat:j2acoyv235awfjkz6w7krvzh44

An Integrated Simulation Environment for Parallel and Distributed System Prototying

Alan D. George, Ryan B. Fogarty, Jeff S. Markwell, Michael D. Miars
1999 Simulation (San Diego, Calif.)  
When high-fidelity models of parallel architecture are coupled with workloads generated from real parallel application code in an execution-driven simulation, the result is a potent design and analysis  ...  existing hardware-in-the-loop (HWIL) to execute real parallel programs on virtual prototypes.  ...  Acknowledgments The support provided by the Office of Naval Research on grant N00014-98-1-0188 is acknowledged and appreciated, as is the SCI equipment support from Dolphin Interconnect Solutions, Inc.  ... 
doi:10.1177/003754979907200502 fatcat:nic2u6qu4rghbkktzbr5hqkvky

HEPAPS: A PCB automatic placement system

Jianguo Xu, Yuchai Gou, Zongkai Lin
1992 Journal of Computer Science and Technology  
This paper discusses automatic mapping methods for concurrent tasks to processors applying graph analysis for the relation among tasks, in which processing and communicating times are incorporated.  ...  Some results obtained with the model and future work lines are presented, particularly, the possibility of obtaining the required optimal number of processors, keeping a constant efficiency level.  ...  The possibility of using a simulation algorithm to predict the execution time of the application to be parallelized on an real architecture was studied.  ... 
doi:10.1007/bf02946164 fatcat:ky2spi22pvfsdmhep6uwwjvn7u

Real-Time Machine Learning: The Missing Pieces [article]

Robert Nishihara, Philipp Moritz, Stephanie Wang, Alexey Tumanov, William Paul, Johann Schleier-Smith, Richard Liaw, Mehrdad Niknami, Michael I. Jordan, Ion Stoica
2017 arXiv   pre-print
over a state-of-the-art execution framework for a representative application.  ...  Machine learning applications are increasingly deployed not only to serve predictions using static models, but also as tightly-integrated components of feedback loops involving dynamic, real-time decision  ...  Acknowledgments We would like to thank Richard Shin for substantial contributions to the development of our prototype.  ... 
arXiv:1703.03924v2 fatcat:4vojlygby5gnpbmziwl63gpb2u

Software architecture for time-constrained machine vision applications

Rubén Usamentiaga, Julio Molleda, Daniel F. García, Francisco G. Bulnes
2013 Journal of Electronic Imaging (JEI)  
Many frameworks and libraries have been proposed or commercialized to simplify the design and tuning of real-time image processing applications.  ...  Real-time image and video processing applications require skilled architects, and recent trends in the hardware platform make the design and implementation of these applications increasingly complex.  ...  Acknowledgments This work was partially supported by the Asturian Regional Ministry of Education and Science under Project No. PC10-03.  ... 
doi:10.1117/1.jei.22.1.013001 fatcat:47tvuzx26fdvrmv73bpe4geokm

Optimal Performance Prediction of ADAS Algorithms on Embedded Parallel Architectures

Romain Saussard, Boubker Bouzid, Marius Vasiliu, Roger Reynaud
2015 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems  
Due to the complexity of these SoCs, predicting if a given algorithm can be executed in real time on a given architecture is not trivial.  ...  These SoCs (System on Chip) are composed of different processing units, with different capabilities, and often with massively parallel computing unit.  ...  Real execution time is t real = 2194µs. B.  ... 
doi:10.1109/hpcc-css-icess.2015.95 dblp:conf/hpcc/SaussardBVR15 fatcat:5f63trlctvgorgsc3kbh5nh7a4
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