1,328 Hits in 3.1 sec

The Entropy of FPGA Reconfiguration

Usama Malik, Oliver Diessel
2006 2006 International Conference on Field Programmable Logic and Applications  
In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device.  ...  We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family.  ...  We define entropy of reconfiguration, H r , to be the entropy of the data source that generates the configuration bitstream required to configure the input circuit onto the tar-get FPGA.  ... 
doi:10.1109/fpl.2006.311223 dblp:conf/fpl/MalikD06 fatcat:4yui2w7bkvd4nn2ti2ylxmxjfi

Pel reconstruction on FPGA-augmented TriMedia

M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, K.A. Vissers
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
the reconfiguration of the RFU, and their associated instructions.  ...  The most important aspects concerning the implementation of the FPGA-mapped VLD-2, IQ-4, and 1-D IDCT units, as well as the organization of the software routines calling these FPGA-mapped computing units  ...  This may reduce the number of reconfigurations when a large FPGA is available.  ... 
doi:10.1109/tvlsi.2004.827594 fatcat:7mmoqvxk45afdm2mpeap2zirsm

Guest Editorial

André DeHon, Mike Hutton
2008 ACM Transactions on Reconfigurable Technology and Systems  
In this inaugural edition of the ACM Transactions on Reconfigurable Technology and Systems, we are pleased to present expanded versions of five papers from the FPGA08 conference, touching on many of these  ...  "The FPGA Conference" remains the dominant forum bringing together all of these different aspects of FPGA design.  ...  In "Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy," Feng and Kaptanoglu explore the use of entropy as a high-level predictor of routability.  ... 
doi:10.1145/1331897.1341292 fatcat:ko6p67wpe5avrdy2pvfsykacme

On-chip and on-line self-reconfigurable adaptable platform: the non-uniform cellular automata case

A. Upegui, E. Sanchez
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Our implementation includes an on-chip soft-processor that generates a partial bitstream, reconfigures the FPGA, and computes the fitness.  ...  In this paper we present a platform for evolving CA by exploiting the partial re-configurability of current commercial FPGAs.  ...  -Compute entropy of the system as the mean entropy for each bit subsequence, with the expression:  ... 
doi:10.1109/ipdps.2006.1639464 dblp:conf/ipps/UpeguiS06 fatcat:ft7uq6pkgvewxgnhegc43xhalu

A real-time permutation entropy computation for EEG signals

Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren
2015 The 20th Asia and South Pacific Design Automation Conference  
In this paper, we implement a reconfigurable FPGA accelerator which could compute multiscale permutation entropy for 128 EEG signals simultaneously in real time.  ...  When it works at 150MHz and the window size is 256, compared with C code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU, the average speedup is 3748.  ...  In [3] , we implemented a reconfigurable FPGA accelerator for the evaluation of permutation entropy, in which the time scale factor is set to 1 constantly.  ... 
doi:10.1109/aspdac.2015.7058926 dblp:conf/aspdac/RenYCZR15a fatcat:ha46jt52ibcsbefxm377fzukma

A Novel Design of Adaptive and Hierarchical Convolutional Neural Networks using Partial Reconfiguration on FPGA [article]

Mohammad Farhadi, Mehdi Ghasemi, Yezhou Yang
2019 arXiv   pre-print
Due to resource limitation on FPGA, the idea of partial reconfiguration has been used to accommodate deep CNNs on the FPGA resources.  ...  Moreover, the implementation of CNNs faces with the size, weight, and energy constraints on the embedded devices.  ...  We propose and implement the idea of partial reconfiguration in the FPGA to map the quantized CNN on the FPGA resources.  ... 
arXiv:1909.05653v1 fatcat:t3mte6volvgvdo2t4u5eydsxei

The Application of Moving Target Defense to Field Programmable Gate Arrays

John Dombrowski, Todd R. Andel, J. Todd McDonald
2016 Proceedings of the 11th Annual Cyber and Information Security Research Conference on - CISRC '16  
FPGA based MTD would allow each FPGA to enhance, rather than weaken, the security of a system.  ...  FPGAs are extremely widespread in addition to becoming more integrated into the systems that they are a part of. This leads to vulnerabilities in almost every system that uses these chips.  ...  ACKNOWLEDGEMENTS This material is based in part upon work supported by the National Science Foundation under Grant No. DUE-1241675.  ... 
doi:10.1145/2897795.2897820 dblp:conf/csiirw/DombrowskiAM16 fatcat:45omp25uxvcojg4zwmm5a4j6ci

A single-chip solution for the secure remote configuration of FPGAs using bitstream compression

Jo Vliegen, Nele Mentcns, Ingrid Verbauwhede
2013 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)  
In particular, bitstream compression in combination with partial reconfiguration is used to avoid the use of an external memory for the storage of the bitstream.  ...  The contribution of this work is that it presents the first complete working system for the secure remote configuration of FPGAs, consisting of a single FPGA chip and an initiating server, given that the  ...  The actual application of the FPGA will be placed in a single reconfigurable partition.  ... 
doi:10.1109/reconfig.2013.6732330 dblp:conf/reconfig/VliegenMV13 fatcat:z67vz4ajpjbs3lyinnikrqp5jq

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Leibo LIU, Dong WANG, Yingjie CHEN, Min ZHU, Shouyi YIN, Shaojun WEI
2016 IEICE transactions on information and systems  
By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding  ...  A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU.  ...  The entropy decoder, whose internal structures are shown in Fig. 7 , is efficiently implemented on fine-grained FPGAs.  ... 
doi:10.1587/transinf.2015edp7369 fatcat:4ixd2sywvvfv5izvwwhpzwl5xe

Self-adaptive image processing using blind image quality assessment technique

K.S. Prasada Kumari
2016 Perspectives in Science  
From implementation point of view, the no-reference scheme is computationally intensive.  ...  The proposed entropy based scheme estimates noise content without any reference image and such a system is vital in situations where uncorrupted image reference is unavailable.  ...  With the availability of commercial FPGAs, image filters are directly evolved in hardware which is implemented using FPGAs.  ... 
doi:10.1016/j.pisc.2016.06.043 fatcat:26subfa5sfdhddtdzjy3u2g5ae

Reconfigurable image registration on FPGA platforms

Mainak Sen, Yashwant Hemaraj, Shuvra S. Bhattacharyya, Raj Shekhar
2006 2006 IEEE Biomedical Circuits and Systems Conference  
Unlike previous FPGA implementations for image registration, the architecture developed in this paper tunes its parallel processing structure adaptively based on relevant characteristics of the input images  ...  In this paper, we present a novel architecture for dynamically-reconfigurable image registration, along with details on the methodology used to derive the architecture.  ...  A major advantage of FPGA technology is the potential for dynamic reconfiguration of the processing structure.  ... 
doi:10.1109/biocas.2006.4600331 fatcat:ti3qtdx5drhrvhad4ohwdlvnri

Advanced AI Hardware Designs Based on FPGAs

Joo-Young Kim
2021 Electronics  
, using a massive amount of data [...]  ...  intelligence (AI) and machine learning (ML) technology enable computers to run cognitive tasks such as recognition, understanding, and reasoning, which are believed to be processes that only humans are capable of  ...  [8] designed a reconfigurable and lightweight coprocessor of the RISC-V for better programmability than array-based accelerators. Gadea-Gironés et al.  ... 
doi:10.3390/electronics10202551 fatcat:ibfguvqxxnamrhlahclb6is5wa

Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements [chapter]

Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens
2004 Lecture Notes in Computer Science  
In this paper we try to reconcile these two requirements by using an FPGA to implement the performance critical parts of a scalable wavelet video decoder.  ...  We find that modern FPGAs offer enough computational power to obtain real-time performance of the decoder, but that reaching the necessary memory bandwidth will be a challenge during this design.  ...  With the proposed evaluation of the performance/cost of FPGA implementations and the study of the reconfiguration possibilities, we will be able to fully grab the performance requirements for reconfigurable  ... 
doi:10.1007/978-3-540-27776-7_22 fatcat:jezxjzu36fbohftag6uxsvfa44

Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications

Darshika G. Perera
2015 Proceedings of the 12th FPGAworld Conference 2015 on - FPGAworld '15  
There are different methods of reconfiguring the hardware on chip dynamically.  ...  FPGA-based dynamic reconfigurable systems are currently the most feasible option to deliver embedded applications that have stringent requirements.  ...  There are different methods of reconfiguring the hardware on chip dynamically.  ... 
doi:10.1145/2889287.2889297 fatcat:3xrcz3p7bja2xet4pnxe5re4ki

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study [chapter]

Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees Vissers
2002 Lecture Notes in Computer Science  
The paper presents a case study on augmenting a TriMedia/CPU64 processor with a Reconfigurable (FPGA-based) Functional Unit (RFU).  ...  The proposed VLD exhibits a latency of 7 TriMedia cycles when mapped on the same FPGA, and utilizes 6 of its embedded array blocks.  ...  Entropy decoder implementation on extended TriMedia The entropy decoder in the extended TriMedia benefits of reconfigurable hardware support.  ... 
doi:10.1007/3-540-45874-3_13 fatcat:7qk6wqzczbhtte5anok6bxwu64
« Previous Showing results 1 — 15 out of 1,328 results