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The Design of Serial ATA Bus Control Chip

Wei Cheng, Zhenghua Tan, Zhiliang Zhu, Guiran Chang
2010 Journal of Computers  
524 JOURNAL OF COMPUTERS, VOL. 5, NO. 4, APRIL 2010 The Design of Serial ATA Bus Control Chip  ...  SYSTEM DESIGN OF HPT183, THE BRIDGE CONNECTION ƒ Wrapping the data from transport layer with SOF, CHIP FOR SERIAL ATA AND PARALLEL ATA CRC, and EOF etc. ƒ Receiving Dword  ... 
doi:10.4304/jcp.5.4.524-532 fatcat:nfvwebfdjjfzllmvgrl7wv5zhm

Standalone General Purpose Data Logger Design and Implementation

N Bello, M Ghraizi, SO Adetona
2015 Nigerian Journal of Technology  
This paper describes the design of a general purpose data logger that is compatible with a variety of transducers, This paper describes the design of a general purpose data logger that is compatible with  ...  a variety of transducers, This paper describes the design of a general purpose data logger that is compatible with a variety of transducers, This paper describes the design of a general purpose data logger  ...  GENERAL ENERAL ENERAL ENERAL P P P PURPOSE URPOSE URPOSE URPOSE D D D DATA ATA ATA ATA L L L LOGGER OGGER OGGER OGGER D D D DESIGN AND ESIGN AND ESIGN AND ESIGN AND I 2.6 The control unit 2.6 The control  ... 
doi:10.4314/njt.v34i2.18 fatcat:dmepds4np5ajhbdkmdpf6pmjkq

Prototype implementation of the embedded PC-based control and DAQ module for TESLA cavity SIMCON

Piotr Roszkowski, Wojciech M. Zabolotny, Krzysztof Kierzkowski, Krzysztof T. Pozniak, Ryszard S. Romaniuk, Stefan Simrock
2005 Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments III  
This board is a result of the new approach to the architecture of measurement systems, where the VME controller is replaced with the embedded PC, to improve the functionality and to reduce cost of the  ...  This paper describes the results obtained with the first prototype of the embedded PC (Axis ETRAX LX MCM) based board for control and data acquisition system, to be used in TESLA controller and simulator  ...  Another shortage of the VME bus is that each rack must be equipped with the bus controller witch increases the cost of the system.  ... 
doi:10.1117/12.610571 fatcat:36aqpevocvhu7pzqkouo3wp43e

A serial communication infrastructure for multi-chip address event systems

Daniel B. Fasnacht, Adrian M. Whatley, Giacomo Indiveri
2008 2008 IEEE International Symposium on Circuits and Systems  
The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125MHz for 32bit  ...  The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125MHz for 32bit  ...  ACKNOWLEDGMENT Some of the ideas presented in this work were inspired by discussions held at the Telluride Neuromorphic Engineering Workshop. Particularly helpful suggestions were provided by V.  ... 
doi:10.1109/iscas.2008.4541501 dblp:conf/iscas/FasnachtWI08 fatcat:2mu3sqxkqrgmnlk6kshaqdh4ue

Data Transfer between Two USB Flash SCSI Disks using a Touch Screen

Anurag A. Chakravorty, Raghwendra J. Suryawanshi
2014 International Journal of Engineering Trends and Technoloy  
This is a user friendly device which uses the most popular bus USB (Universal Serial Bus) with Type-A connector. It is governed by the USB 2.0 Protocol.  ...  One of the major advantage of this device is its portability.  ...  The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link de facto standard, named by Motorola that operates in full duplex mode.  ... 
doi:10.14445/22315381/ijett-v13p215 fatcat:4ikzhdtqevayrmdbeil3gixo5i

Hardware-Software Monitoring Techniques for Dynamic Partial Reconfigurable Embedded Systems

Xiao-Wei Wang, Wei-Nan Chen, Cheng-Lian Peng, Hong-jun You
2008 2008 International Conference on Embedded Software and Systems Symposia  
Dynamical partial reconfigurable monitor module based on the reconfigurablity of the hardware platform and the implement methods were proposed in this paper, which decrease the chip's area consumption  ...  Dynamic partial reconfigurable embedded system includes at least one reconfigurable device, which is emerging as the new paradigm for satisfying the simultaneous demand for application performance and  ...  The CODEC chip samples audio signal through Line In jack at 48000 Hz and sends sampled data serially to AC97 controller.  ... 
doi:10.1109/icess.symposia.2008.10 fatcat:z5mgaogypvflfpnlz4rgohkt24


Y. Amar Babu .
2016 International Journal of Research in Engineering and Technology  
network-On-chip.  ...  To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability, system-On-Chip will combine several number of processors cores and other IPs with  ...  The modified network interface for the spatial division multiplexing based network on chip has special control block that will be used to control in coming 32 bit data from different channels of soft IP  ... 
doi:10.15623/ijret.2016.0502062 fatcat:pymil34o5rhjrgpt2rn2zb4zly

Technology and Terms [chapter]

Corey Gough, Ian Steiner, Winston Saunders
2015 Energy Efficient Servers  
SVID Serial VID is a serial communication bus between the processor package and the voltage regulator controllers. TC0/TC1/TC3/TC6 Describes a specific thread-level C-state.  ...  SATA Serial ATA is a common protocol for connecting disks to a storage controller. SEL The System Event Log is a centralized event log used by management firmware.  ... 
doi:10.1007/978-1-4302-6638-9_10 fatcat:g7qmc24w2zgdtlzmsjhomuylxe

Development of Algorithm to Enhance the Security Feature of SATA on Solid State Drives

2019 International Journal of Engineering and Advanced Technology  
Also, implementation of algorithm to enhance the security of Solid-state drives in terms of user authentication, access control and media recovery from ATA security feature set.  ...  Now a day's quantity of data growing day by day accordingly the size of storage media is also increasing rapidly.  ...  The Serial ATA Commands Logger captures the ATA commands between the attached storage devices and the host bus adopter also sends the captured commands to a serial console.  ... 
doi:10.35940/ijeat.f1039.0886s19 fatcat:li2nueo5vfdbzpfnkt2j6x7hh4

A single-chip LSI high-speed functional tester

J. Miyamoto, M.A. Horowitz
1987 IEEE Journal of Solid-State Circuits  
A prototype chip designed by 3um CMOS contains 64.5K transistors in a die size of 9.2mm by 7.9mm, and dissipates less than 300mW at an operating frequency of 10MHz. DTIC S ELECTE M10 i987 1°~.  ...  As shown in Fig. 1 , the DGR is composed of three main parts: memory, address control, and DUT(Device Under Test) pin control. The memory stores the test vectors for the DUT.  ...  Acknowledgements The development of the DGR was partially supported by the Defense Advanced Project Research Agency under Contract No. MDA903-83-C-0335. Mr.  ... 
doi:10.1109/jssc.1987.1052818 fatcat:zmslo2fhl5ab7mymv5atg4aqta

The Design of a Portable Control Module Based on TMS320C6748 and FPGA

Qing-zhong JIA, Zong-rui LIU
2016 DEStech Transactions on Engineering and Technology Research  
And we also use FPGA plus the PCI bridge chip, UART transceiver and CAN transceiver to realize the system control module.  ...  This control module includes interactive module, memory module and communication module. The control module has the characteristics of low power consumption, high reliability and low cost.  ...  Low cost: the master control chips costs are less than the general-purpose CPU. The heat is less, so the cooling device of the peripheral requires low and the cost will be reduced.  ... 
doi:10.12783/dtetr/amita2016/3665 fatcat:t3gqq7ucjfdhhgpt75pw32nnru

Storage topologies

R. Griswold
2002 Computer  
While not as far in development as Serial ATA, Serial Attached SCSI is the newest solution to the parallel bus problem for SCSI proponents.  ...  Initial PCI-based host controllers that ship in support of Serial ATA will be backward compatible with parallel ATA, so that existing operating systems can function.  ... 
doi:10.1109/mc.2002.1106180 fatcat:yawzcjfe3ncdtbdquzbbrcf2g4

Toward a Software Infrastructure for the Cyclops-64 Cellular Architecture

Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. Gao
2006 20th International Symposium on High-Performance Computing in an Advanced Collaborative Environment (HPCS'06)  
of the C64 TVM; (3) the system software for host control.  ...  The C64 system is the latest version of the Cyclops cellular architecture that consists of a large number of compute nodes each employs a multiprocessor-on-a-chip architecture with 160 hardware thread  ...  Acknowledgments We acknowledge the support from IBM, ETI, the Department of Defense, the Department of Energy (DE-FC02-01ER25503), the National Science Foundation (CNS-0509332), and other government sponsors  ... 
doi:10.1109/hpcs.2006.48 dblp:conf/hpcs/CuvilloZHG06 fatcat:o6356mx7rrabph75vxiqo7zb6u

Design and Implementation of Wide-area Monitoring System for Oceanic Pasture

Fa-Bin Li, Yao Shi, Hui Li, Ya-Fei Yang, Peng-Xiang Li
2017 International Journal of u- and e- Service, Science and Technology  
According to the characteristics of aquaculture industry in the South China Sea, a wide-area multi-parameter monitoring system for oceanic pasture was designed.  ...  For the aquatic production and quality of the oceanic pasture, the quality of water is an important factor.  ...  The baseplate of the ZigBee module has the ability of transforming USB (Universal Serial Bus) to serial port and it provides 3.3V power to 170MHz wireless serial port module.  ... 
doi:10.14257/ijunesst.2017.10.3.08 fatcat:md42te5jefdp5ov7tpdekribqe

The Data Processor of the EUSO-SPB2 Telescopes [article]

Giuseppe Osteria, Valentina Scotti, Francesco Perfetto
2019 arXiv   pre-print
In this paper we describe the main components of the system and the design developed for the new mission.  ...  The DP is the component of the electronics system which performs data management and instrument control for each of the two telescopes.  ...  and others are in advanced stage of design. The integration and the test of the DP system is planned for the beginning of 2020.  ... 
arXiv:1909.01680v1 fatcat:25oyr3clk5halgcuqjjjukhgei
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