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A Rational Deconstruction of Landin's SECD Machine
[chapter]
2005
Lecture Notes in Computer Science
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In this article, we deconstruct the SECD machine into a λ-interpreter, i.e., an evaluation function, and we reconstruct λ-interpreters into a variety of SECD-like machines. ...
Landin's SECD machine was the first abstract machine for the λcalculus viewed as a programming language. ...
Acknowledgments The rational deconstruction presented here arose because of a discussion with Mayer Goldberg in July 2002, at the occasion of our joint work on compilation and decompilation [3] . ...
doi:10.1007/11431664_4
fatcat:5pm6mgbdsbdunlypm4aneygeoa
Dependability Analysis of Data Storage Systems in Presence of Soft Errors
2019
IEEE Transactions on Reliability
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2021 pre-print arXiv:2112.12520v1 fatcat:y2m2kww5czh45bfer7rk6nsz3i
To this end, we implemented the major functions of a typical data storage system controller, running on a full stack of storage system operating system, and developed a framework to perform fault injection ...
We then propose a new metric, Storage System Vulnerability Factor (SSVF), to accurately capture the impact of soft errors in storage systems. ...
Hence, valid tag A is changed
• LINE MODIFIED: The cache line is modified. ...
doi:10.1109/tr.2018.2888515
fatcat:ycwhs5d4frbl5dvfrdvolrjhge
Operating SECDED-based caches at ultra-low voltage with FLAIR
2013
2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
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FLAIR leverages the correction features of existing SECDED code to greatly improve on simple two-way replication. ...
We exploit the observation that only a small percentage of cache lines have multi-bit failures. ...
ACKNOWLEDGMENTS Thanks to Wei Wu for discussions on Multi-bit Error Correction Code. Moinuddin Qureshi is supported by NetApp Faculty Fellowship and Intel Early Career Award. ...
doi:10.1109/dsn.2013.6575314
dblp:conf/dsn/QureshiC13
fatcat:6hxzs2xcl5flfgw2lm2uxcyv4m
Using ECC DRAM to Adaptively Increase Memory Capacity
[article]
2017
arXiv
pre-print
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In this paper, we propose Capacity- and Reliability-Adaptive Memory (CREAM), a hardware mechanism that adapts error correcting DRAM modules to offer multiple levels of error protection, and provides the ...
This additional chip expands the raw capacity of a DRAM module by 12.5%, but the applications are unable to use any of this extra capacity, as it is used exclusively to provide reliability for all data ...
The small performance drops for CREAM occur when there is a balance between the amount of SECDED-covered DRAM and correction-free DRAM (the worst performance occurs at 60% SECDED coverage), because a SECDED-covered ...
arXiv:1706.08870v2
fatcat:mmgj6gdlzrcvtjg6dn4zldzqyy
A Rational Deconstruction of Landin's SECD Machine with the J Operator
2008
Logical Methods in Computer Science
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We also identify that the dump component of the SECD machine is managed in a callee-save way. ...
We present a family of evaluation functions corresponding to this extension of the SECD machine, using a series of elementary transformations (transformation into continu-ation-passing style (CPS) and ...
Lawall, Johan Munk, Kristian Støvring, and the anonymous reviewers of IFL'05 and LMCS for comments. ...
doi:10.2168/lmcs-4(4:12)2008
fatcat:3khwwl6etjfltigkktvvg4jya4
A Rational Deconstruction of Landin's J Operator
2006
BRICS Report Series
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We present a family of compositional evaluation functions corresponding to this extension of the SECD machine, using a series of elementary transformations (transformation into continuation-passing style ...
Landin's J operator was the first control operator for functional languages. It was specified with an extension of the SECD machine, which was the first abstract machine for functional languages. ...
Lawall, Kristian Støvring, and the anonymous reviewers of IFL'05 for comments. ...
doi:10.7146/brics.v13i17.21922
fatcat:n7dvdb7nrzhtfmectjj6ctbula
Dynamic error mitigation in NoCs using intelligent prediction techniques
2016
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
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We propose to utilize machine learning techniques to train a decision tree which can be used to predict faults efficiently in the network. ...
Our results indicate that, on average, we can accurately predict timing errors 60.6% better than a static single error correction and double error detection (SECDED) technique resulting in an average 26.8% ...
We would like to thank the anonymous reviewers for their valuable feedback. ...
doi:10.1109/micro.2016.7783734
dblp:conf/micro/DiTomasoBKL16
fatcat:ryihgdiumfdire5vjxk7yfvkae
Reducing cache power with low-cost, multi-bit error-correcting codes
2010
SIGARCH Computer Architecture News
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error-correcting (SECDED) code (2% overhead). ...
Hi-ECC includes additional optimizations that allow us to amortize the storage cost of the code over large data words, providing the benefit of multi-bit correction at same storage cost as a single-bit ...
machine. ...
doi:10.1145/1816038.1815973
fatcat:lacazxmerrdcdb536ouz7u76nm
System implications of memory reliability in exascale computing
2011
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis on - SC '11
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The use of error correction codes (ECC) and checkpointing are two effective approaches to fault tolerance. ...
The use of error correction codes (ECC) and checkpointing are two effective approaches to fault tolerance. ...
Although 64-bit SECDED is still possible at exascale, it wastes lots of machine time and power since the EDP overhead for checkpointing is more than 130% of the native execution. ...
doi:10.1145/2063384.2063445
dblp:conf/sc/LiCHMKBRJ11
fatcat:rjmhvkwzcfhqpewfdci2tegq3y
Reducing cache power with low-cost, multi-bit error-correcting codes
2010
Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10
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error-correcting (SECDED) code (2% overhead). ...
Hi-ECC includes additional optimizations that allow us to amortize the storage cost of the code over large data words, providing the benefit of multi-bit correction at same storage cost as a single-bit ...
machine. ...
doi:10.1145/1815961.1815973
dblp:conf/isca/WilkersonACWSL10
fatcat:b3figxmaxre4hnvzlvn5nagzxu
A Rational Deconstruction of Landin's J Operator
2006
BRICS Report Series
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), we present a compositional evaluation function corresponding to this extension of the SECD machine. ...
Landin's J operator was the first control operator for functional languages, and was specified with an extension of the SECD machine. ...
Lawall, Kristian Støvring, and the anonymous reviewers of IFL'05 for comments. ...
doi:10.7146/brics.v13i4.21910
fatcat:23bkms56nvbfzjlgross556vhm
A Rational Deconstruction of Landin's J Operator
[chapter]
2006
Lecture Notes in Computer Science
Preserved Fulltext
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The file type is application/pdf.
), we present a compositional evaluation function corresponding to this extension of the SECD machine. ...
Landin's J operator was the first control operator for functional languages, and was specified with an extension of the SECD machine. ...
Lawall, Kristian Støvring, and the anonymous reviewers of IFL'05 for comments. ...
doi:10.1007/11964681_4
fatcat:ygwo3ji5sncuvhkparwlw7irbe
Energy-efficient cache design using variable-strength error-correcting codes
2011
SIGARCH Computer Architecture News
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In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. ...
In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. ...
The hardware overhead of characterization is trivial compared to the cache size, and involves a simple state machine with tens of state elements and a few gates. ...
doi:10.1145/2024723.2000118
fatcat:mue6nkv4gzhttmxwr2otj2sv5m
Energy-efficient cache design using variable-strength error-correcting codes
2011
Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11
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In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. ...
In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. ...
The hardware overhead of characterization is trivial compared to the cache size, and involves a simple state machine with tens of state elements and a few gates. ...
doi:10.1145/2000064.2000118
dblp:conf/isca/AlameldeenWCWWL11
fatcat:bhrzkqu3lrggfm543dg4jzozd4
The categorical abstract machine
1987
Science of Computer Programming
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The machine is called categorical abstract machine or CAM. The CAM is easier to grasp and prove than the SECD machine. ...
The only saving mechanism is a stack containing pointers on code or on the graph. Abstractions are handled in the very same way as in P. Landin's SECD machine, using closures. ...
The CAM has the conceptually simplest approach (which is reflected by the simplicity of the correctness proof, as compared with the proof of correctness of the SECD machine [18] ,) ), but the price ...
doi:10.1016/0167-6423(87)90020-7
fatcat:hkajotn7s5e3jdeherd7drbu3q
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