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The completeness of a hardware inference system [chapter]

Zheng Zhu, C-J Seger
1994 Lecture Notes in Computer Science  
These inference rules were also proven sound. In this paper we show that, with one additional inference rule, the inference system is complete.  ...  Here, complete means that any formula A =~ C, that is valid in every model satisfying some collection 9 of STE assertions, can be derived from ~ by a finite applications of the inference rules.  ...  Acknowledgments We are indebted to the reviewers who have made many helpful and constructive remarks on an earlier draft of this paper.  ... 
doi:10.1007/3-540-58179-0_62 fatcat:64dsnnla3fhaxk5bjzeph6a63u

Hardware for Fuzzy Logic Applications

C. Kasper, H.-J. Zimmermann
1994 Journal of Japan Society for Fuzzy Theory and Systems  
tailored for a specific customer and which Complete System an especially high number of sensor signals and which accordingly can address a high number of actors.  ...  Genuine"hardware is defined as a system in which the different fuzzy operations are implemented directly in the hardware.  ... 
doi:10.3156/jfuzzy.6.3_451 fatcat:fkdpvbnus5fchdztyvph2floye

Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network

Maolin Wang, Kelvin C. M. Lee, Bob M. F. Chung, Sharatchandra Varma Bogaraju, Ho-Cheung Ng, Justin S. J. Wong, Ho Cheung Shum, Kevin K. Tsia, Hayden Kwok-Hay So
2021 IEEE Transactions on Neural Networks and Learning Systems  
The proposed design performs inference operations on a stream of individual images as they are produced and has a deeply pipelined hardware design that allows all layers of a quantized convolutional neural  ...  Using the case of label-free classification of human peripheral blood mononuclear cell (PBMC) subtypes as a proof-of-concept illustration, our system achieves an ultralow classification latency of 34.2  ...  Using an image size of 336 × 336 pixels, our CNN completed inference operations in 7436 cycles, which translated to 30.0 µs when the FPGA system was running at 247.8 MHz.  ... 
doi:10.1109/tnnls.2020.3046452 fatcat:uc5uzptnjjek3cbdg4b64rmvsy

Extending formal reasoning with support for hardware diagrams [chapter]

Kathi Fisler
1995 Lecture Notes in Computer Science  
We demonstrate some advantages of formally supporting diagrams in hardware verification systems via a simple example from the verification of a single-pulser.  ...  Diagrams have been left as an informal tool in hardware reasoning, thus rendering them unacceptable representations within formal reasoning systems.  ...  A previous attempt at defining a heterogeneous logic for hardware, aiong with more complete arguments supporting the use of diagrams in hardware formal methods, is presented in [8] .  ... 
doi:10.1007/3-540-59047-1_57 fatcat:muxh47msxzgtppcm2esa5pjtye

Research on the Lightweight Deployment Method of Integration of Training and Inference in Artificial Intelligence

Yangyang Zheng, Bin He, Tianling Li
2022 Applied Sciences  
Then, the method of converting the network model into hardware logic implementation was studied, and the model parameters were transferred from the processing system of the device to the hardware accelerator  ...  to improve the flexibility and robustness of the system.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/app12136616 fatcat:a3p3aavl4rcubgmpnx7sma2mcm

InferBench: Understanding Deep Learning Inference Serving with an Automatic Benchmarking System [article]

Huaizheng Zhang, Yizheng Huang, Yonggang Wen, Jianxiong Yin, Kyle Guan
2021 arXiv   pre-print
To accomplish benchmark-related tasks, the developers only need to prepare a configuration file consisting of a few lines of code.  ...  Finally, developers can leverage many analysis tools and models in our system to gain insights into the trade-offs of different system configurations.  ...  Once the inference is completed, the predictions will be post-processed (either in a server or a client) and displayed to the end-users.  ... 
arXiv:2011.02327v3 fatcat:74qfcxlwmbc7tifndzbnl3igki

Hardware counter driven on-the-fly request signatures

Kai Shen, Ming Zhong, Sandhya Dwarkadas, Chuanpeng Li, Christopher Stewart, Xiao Zhang
2008 Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII  
Our key finding is that effective request signatures may be constructed using a small amount of hardware statistics while the request is still in an early stage of its execution.  ...  We address the challenges of selecting hardware counter metrics for signature construction and providing necessary operating system support for per-request statistics management.  ...  Request Property Inference Accuracy We evaluate the effectiveness of hardware counter metric driven on-the-fly request property inference.  ... 
doi:10.1145/1346281.1346306 dblp:conf/asplos/ShenZDLSZ08 fatcat:6blqfstlvrhdzhjqdksbho2m5a

Hardware counter driven on-the-fly request signatures

Kai Shen, Ming Zhong, Sandhya Dwarkadas, Chuanpeng Li, Christopher Stewart, Xiao Zhang
2008 ACM SIGOPS Operating Systems Review  
Our key finding is that effective request signatures may be constructed using a small amount of hardware statistics while the request is still in an early stage of its execution.  ...  We address the challenges of selecting hardware counter metrics for signature construction and providing necessary operating system support for per-request statistics management.  ...  Request Property Inference Accuracy We evaluate the effectiveness of hardware counter metric driven on-the-fly request property inference.  ... 
doi:10.1145/1353535.1346306 fatcat:3wmyhhxunrhg5c4n7zurxc7tpm

Hardware counter driven on-the-fly request signatures

Kai Shen, Ming Zhong, Sandhya Dwarkadas, Chuanpeng Li, Christopher Stewart, Xiao Zhang
2008 SIGPLAN notices  
Our key finding is that effective request signatures may be constructed using a small amount of hardware statistics while the request is still in an early stage of its execution.  ...  We address the challenges of selecting hardware counter metrics for signature construction and providing necessary operating system support for per-request statistics management.  ...  Request Property Inference Accuracy We evaluate the effectiveness of hardware counter metric driven on-the-fly request property inference.  ... 
doi:10.1145/1353536.1346306 fatcat:kv2oc2v6a5dhng64ujj4lymv7u

Hardware counter driven on-the-fly request signatures

Kai Shen, Ming Zhong, Sandhya Dwarkadas, Chuanpeng Li, Christopher Stewart, Xiao Zhang
2008 SIGARCH Computer Architecture News  
Our key finding is that effective request signatures may be constructed using a small amount of hardware statistics while the request is still in an early stage of its execution.  ...  We address the challenges of selecting hardware counter metrics for signature construction and providing necessary operating system support for per-request statistics management.  ...  Request Property Inference Accuracy We evaluate the effectiveness of hardware counter metric driven on-the-fly request property inference.  ... 
doi:10.1145/1353534.1346306 fatcat:ofuzmoeycvhkdiriqijd3ro4z4

SCALABLE ARCHITECTURE FOR HIGH-SPEED MULTIDIMENSIONAL FUZZY INFERENCE SYSTEMS

INÉS DEL CAMPO, JAVIER ECHANOBE, KOLDO BASTERRETXEA, GUILLERMO BOSQUE
2011 Journal of Circuits, Systems and Computers  
This paper presents a scalable architecture suitable for the implementation of high-speed fuzzy inference systems on reconfigurable hardware.  ...  As a prototyping example, we implemented a complex fuzzy controller for a vehicle semi-active suspension system composed of four three-input FIS on a single FPGA of the Xilinx's Virtex 5 device family.  ...  Acknowledgments The authors would like to thank the Basque Country Government and Spanish Ministry of Science and Innovation (MICINN) for supporting this work under Grants S-PE08UN49 and GIC07/138-IT-353  ... 
doi:10.1142/s0218126611007359 fatcat:5xcs5lscbfbshjhowix7fzosme

A Structured Hardware Software Architecture for Peptide Based Diagnosis of Baylisascaris Procyonis Infection (ICIAfS14) [article]

S. M. Vidanagamachchi, S.D. Dewasurendra, R. G. Ragel, M. Niranjan
2014 arXiv   pre-print
In the current paper a model-based hardware acceleration of a structured and practical inference approach is developed and validated on a mass spectrometry experiment of realistic size.  ...  This is exacerbated by the fact that, in general, a given protein cannot be defined by a fixed sequence of amino acids due to the existence of splice variants and isoforms of that protein.  ...  Further they have implemented the complete set of processes in the inference workflow in hardware [6] .  ... 
arXiv:1412.7811v1 fatcat:2dbbnciuobgvzbgvj7rmjjasou

Deep Graph Learning for Search & Recommender Systems

Bee-Chung Chen, Andrew Zhai
2022 Zenodo  
Most state-of-the-art search and recommender systems use neural networks to learn representations of entities like users, queries and content items.  ...  In this talk, we describe the architecture of deep-learning-based search and recommender systems, show how to apply GNNs learned from billions of nodes and edges to these systems to improve their performance  ...  sampling on the fly ○ Solution: Move sampling out of training / inference • Sample Method: Random walks (50 neighbors) • Data Prep: ○ Compute 3B * 50 random walk in a daily workflow ○ Materializes self  ... 
doi:10.5281/zenodo.6507203 fatcat:zerrpyba5bb7nl2eaoh6aink6e

Hardware accelerated protein inference framework [article]

S.M. Vidanagamachchi, S.D. Dewasurendra, R.G. Ragel
2014 arXiv   pre-print
Protein inference plays a vital role in the proteomics study. Two major approaches could be used to handle the problem of protein inference; top-down and bottom-up.  ...  The framework is developed on an FPGA where hardware software co-design techniques are used to accelerate the computationally intensive parts of the protein inference process.  ...  This type of hardware implementation has not been done in the past. The implementation of the prototype is completed on a Cyclone II FPGA chip by Altera.  ... 
arXiv:1403.1319v1 fatcat:rb6mcmljm5e4nnj2zl5htlatca

Seeker: Synergizing Mobile and Energy Harvesting Wearable Sensors for Human Activity Recognition [article]

Cyan Subhra Mishra, Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan
2022 arXiv   pre-print
Seeker uses a store-and-execute approach to complete a subset of inferences on the EH sensor node, reducing communication with the mobile host.  ...  Seeker performs HAR with 86.8% accuracy, surpassing the 81.2% accuracy of a state of the art approach. Moreover, by using AAC, it lowers the communication data volume by 8.9×.  ...  Fig. 2a shows that a state-of-the-art system still only finishes ≈ 58.7% of the inferences scheduled on a sensor.  ... 
arXiv:2204.13106v1 fatcat:ryfubvnskrbarjj7kwdalia2f4
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