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The Challenge of Time-Predictability in Modern Many-Core Architectures

Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, Andrea Marongiu, Marc Herbstritt
2014 Worst-Case Execution Time Analysis  
of many-core platforms in a predictable way.  ...  The convergence of these two domains towards systems requiring both high performance and a predictable time-behavior challenges the capabilities of current hardware architectures.  ...  The challenge of time-predictability in modern many-core architectures problem was already central in single-core platforms but is now further exacerbated in a multi/many-core setting where low-level hardware  ... 
doi:10.4230/oasics.wcet.2014.63 dblp:conf/wcet/NelisYPFBQVM14 fatcat:lk7ci2u6efcenfyvn3jtitht34

How to stop under-utilization and love multicores

Anastasia Ailamaki, Erietta Liarou, Pinar Tözün, Danica Porobic, Iraklis Psaroudakis
2014 Proceedings of the 2014 ACM SIGMOD international conference on Management of data - SIGMOD '14  
In addition, it examines the sources of under-utilization in a modern processor and presents insights and hardware/software techniques to better exploit the microarchitectural resources of a processor  ...  micro-architectural features, (2) exploiting the explicit/horizontal parallelism provided by multicores, and (3) achieving predictively efficient execution despite the variability in communication latencies  ...  Servers with multiple processors and non-uniform memory access (NUMA) design present additional challenge do data management systems, many of which were designed with implicit assumptions that core-to-core  ... 
doi:10.1145/2588555.2588892 dblp:conf/sigmod/AilamakiLTPP14 fatcat:rkcyemhxhvh45d6gbzorxfinvi

How to stop under-utilization and love multicores

Anastasia Ailamaki, Erietta Liarou, Pinar Tozun, Danica Porobic, Iraklis Psaroudakis
2015 2015 IEEE 31st International Conference on Data Engineering  
In addition, it examines the sources of under-utilization in a modern processor and presents insights and hardware/software techniques to better exploit the microarchitectural resources of a processor  ...  micro-architectural features, (2) exploiting the explicit/horizontal parallelism provided by multicores, and (3) achieving predictively efficient execution despite the variability in communication latencies  ...  Servers with multiple processors and non-uniform memory access (NUMA) design present additional challenge do data management systems, many of which were designed with implicit assumptions that core-to-core  ... 
doi:10.1109/icde.2015.7113419 dblp:conf/icde/AilamakiLTPP15 fatcat:v6zdaujg6zat3oqb7zjstbts74

Towards software performance engineering for multicore and manycore systems

Heiko Koziolek, Steffen Becker, Jens Happe, Petr Tuma, Thijmen de Gooijer
2014 Performance Evaluation Review  
In the era of multicore and manycore processors, a systematic engineering approach for software performance becomes more and more crucial to the success of modern software systems.  ...  Acknowledgements We are grateful to the team at Schloss Dagstuhl for hosting the seminar that led to this paper. We thank all participants for their contributions and the engaging discussions.  ...  An important feature that affects software performance in many modern systems is virtualization.  ... 
doi:10.1145/2567529.2567531 fatcat:j24fiw7ulrfedc3vmce7kcy3ri

Strategies for improving performance and energy efficiency on a many-core

Elkin Garcia, Guang Gao
2013 Proceedings of the ACM International Conference on Computing Frontiers - CF '13  
efficiency of modern many-core architectures.  ...  New many-core architectures are characterized not only by the large amount of processing elements but also by the large number and heterogeneity of resources.  ...  ACKNOWLEDGEMENTS This work has been made possible by the generous support of the NSF through research grants CCF-0833122, CCF-0925863, CCF-0937907, CNS-0720531, and OCI-0904534.  ... 
doi:10.1145/2482767.2482779 dblp:conf/cf/GarciaG13 fatcat:n2syt3shvndjxazsdjyggacrka

Multicore distributed processing architecture with Miss Table in radar systems for real-time severe weather analysis

Abu Asaduzzaman, Wajid Hassan, Darryl Koivisto
2011 2011 IEEE RadarCon (RADAR)  
In spite of the fact that multicore architecture improves performance, it poses some serious challenges including execution time unpredictability which is not acceptable for real-time weather analysis.  ...  In this work, we model and simulate a popular Intel-like multicore architecture with Miss Table ( MT) and investigate the effectiveness of the multicore architectures for real-time severe weather analysis  ...  Studies indicate that multicore computing architecture has the potential to fulfill the requirements of high processing speed of modern radar systems [5, 6] .  ... 
doi:10.1109/radar.2011.5960541 fatcat:2sxkqggv5zfu3gmastctpemnqa

MCAD: Beyond Basic-Block Throughput Estimation Through Differential, Instruction-Level Tracing [article]

Min-Yih Hsu, David Gens, Michael Franz
2022 arXiv   pre-print
In this paper, we present MCAD, a novel and lightweight timing analysis framework that can identify the effects of code changes on the microarchitectural level for binary programs.  ...  To the best of our knowledge this represents an entirely new capability that reduces turnaround times for differential throughput estimation by several orders of magnitude compared to state-of-the-art  ...  However, the core analysis component in our design can support other throughput analysis engines in principle, which would allow us to predict timing effects of a number of optimizations in modern processors  ... 
arXiv:2201.04804v1 fatcat:sdxb7vhdxrfbznh2da6b7lihuu

Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441)

Tulika Mitra, Jürgen Teich, Lothar Thiele, Marc Herbstritt
2017 Dagstuhl Reports  
Instead of best-effort and average performance, these real-time applications demand timing predictability and/or security levels specifiable on a per-application basis.  ...  If the overhead can be kept low, there is a chance that adaptive isolation, the title of the seminar, may enable the adoption of MPSoC technology for many new application areas of embedded systems.  ...  topic of the seminar as well as to the list of participants.  ... 
doi:10.4230/dagrep.6.10.120 dblp:journals/dagstuhl-reports/MitraTT16 fatcat:xvvcpukdp5ftrfeiz5ar5xksse

Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities [article]

Mohamed Hassan
2017 arXiv   pre-print
Seizing these opportunities is unattainable without addressing the associated challenges.  ...  Furthermore, heterogeneity of MPSoCs presents exceptional opportunities to satisfy the conflicting requirements of MCS.  ...  This interference is a challenge for real-time systems because operations of one core affect the temporal behaviour of other cores, which complicates the timing analysis of the system.  ... 
arXiv:1706.07429v1 fatcat:5jqdhovqpba5vbagwsrxc6e2fa

Editorial

Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag
2014 Design automation for embedded systems  
The connecting piece of all heterogeneous hardware components is the interconnect architecture.  ...  With their increasing number of processing nodes these interconnects pose significant challenges to the designer.  ...  In particular, these papers include the following topics: -Centaur: A Hybrid Network-on-Chip Architecture Utilizing Micro-Network Fusion deals with the design of a fused NoC architecture composed of a  ... 
doi:10.1007/s10617-014-9136-7 fatcat:qmjth3zpmjefrgdxaactfvcyje

Design Challenges in Hardware Development of Time-Sensitive Networking: A Research Plan

Adnan Ghaderi, Masoud Daneshtalab, Mohammad Ashjaei, Mohammad Loni, Saad Mubeen, Mikael Sjödin
2019 CPS Summer School  
In this paper, we present a research plan for developing novel techniques to support a parameterized and modular hardware IP core of the multi-stage TSN switch fabric in VHSIC (Very High Speed Integrated  ...  We present the challenges on the way towards the mentioned goal.  ...  Acknowledgement This work is supported by the Swedish Governmental Agency for Innovation Systems (VINNOVA) through the DESTINE project.  ... 
dblp:conf/cpsschool/GhaderiDALMS19 fatcat:6ie5k7gw2favrf6xxlvup5dcrq

Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures

Matthias Becker, Dakshina Dasari, Vincent Nelis, Moris Behnam, Luis Miguel Pinho, Thomas Nolte
2015 2015 Euromicro Conference on Digital System Design  
This update came as a response to the steady increase of the number and complexity of the software functions embedded in modern vehicles, which call for the computing power of multicore execution environments  ...  In this paper, we enumerate and analyze the design options and the challenges of porting AUTOSAR-based automotive applications onto multicore platforms.  ...  ACKNOWLEDGMENT The work presented in this paper was partially supported by the Swedish Knowledge Foundation via the research project PREMISE and by National Funds through FCT/MEC (Portuguese Foundation  ... 
doi:10.1109/dsd.2015.63 dblp:conf/dsd/BeckerDNBPN15 fatcat:bfydxujl2zewhgbsfnftp2achy

A PRET architecture supporting concurrent programs with composable timing properties

Isaac Liu, Jan Reineke, Edward A. Lee
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
This paper describes a realization of PRET, a class of computer architectures designed for timing predictability.  ...  In order to improve design time and efficiency of systems, large scale system design is often split into the design of separate functions, which are later integrated together.  ...  Among those challenges, this paper deals with timing composability and timing predictability at the computer architecture level.  ... 
doi:10.1109/acssc.2010.5757922 fatcat:tbqmh3mmjngq3f5gwi75mcugky

High-Performance Embedded Architecture and Compilation Roadmap [chapter]

Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O'Boyle, Dionisios Pnevmatikatos, Alex Ramirez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
2007 Lecture Notes in Computer Science  
The roadmap details several of the key challenges that need to be tackled in the coming decade, in order to achieve scalable performance in multi-core systems, and in order to make them a practical mainstream  ...  Per theme, a list of challenges is identified. In total 55 key challenges are listed in this roadmap.  ...  Single Core Architecture Many of the classical uniprocessor trade-offs of the last 20 years will have to be reconsidered when uniprocessors are used as building blocks in a multi-core system.  ... 
doi:10.1007/978-3-540-71528-3_2 fatcat:ywmebvj7wrfb3ojghsjs4w3fy4

The Multi-Core Era - Trends and Challenges [article]

Peter Tröger
2008 arXiv   pre-print
Due to physical limitations, this 'free lunch' of speedup has come to an end. The following article gives a summary and bibliography for recent trends and challenges in CMP architectures.  ...  It discusses how 40 years of parallel computing research need to be considered in the upcoming multi-core era.  ...  or many-core processor design.  ... 
arXiv:0810.5439v1 fatcat:p67elbfj2vf6xhonekhmkelpva
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