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The ARMv8 simulator

Tao Jiang, Lixin Zhang, Lele Zhang, Rui Hou, Yi Zhang, Qianlong Zhang, Lin Chai, Jing Han, Wuxiang Zhang, Cong Wang
2013 Proceedings of the 27th international ACM conference on International conference on supercomputing - ICS '13  
•No ARMv8 performance simulator available •Goal of Our ARMv8 Simulator -Easy to use -Easy to debug -Reliable -Accurate -Multiple CPU models -Power simulation •It is the first open source ARMv8 performance  ...  The first ARMv8 CPU are due in 2014 !  ...  •No ARMv8 performance simulator available •Goal of Our ARMv8 Simulator -Easy to use -Easy to debug -Reliable -Accurate -Multiple CPU models -Power simulation •It is the first open source ARMv8  ... 
doi:10.1145/2464996.2467287 dblp:conf/ics/JiangZHZZCHZWZ13 fatcat:phqwsbp4qzge3nwu3gl3una42y

Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications

Alexandra Ferreoon, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru
2017 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
However, as HPC systems reach exascale proportions, the cost of simulation increases, since simulators themselves are largely single-threaded.  ...  We demonstrate a total simulation time reduction of up to 178x, whilst keeping the error below 2.3% for both cycles and instructions.  ...  ACKNOWLEDGEMENTS The authors would like to thank Stephan Diestelhorst, Chris Adeniyi-Jones, Eric Van Hensbergen, Jonathan Beard and Charles García-Tobin for their feedback and support at the different  ... 
doi:10.1109/ispass.2017.7975275 dblp:conf/ispass/FerreronJBR17 fatcat:5emsdpjxjvgbnhzwpt33mpkcnq

Extensive evaluation of programming models and ISAs impact on multicore soft error reliability

Felipe da Rosa, Vitor Bandeira, Ricardo Reis, Luciano Ost
2018 Proceedings of the 55th Annual Design Automation Conference on - DAC '18  
ARMv8 rather than in the ARMv7.  ...  of the same benchmarks using both ARMv7 and ARMv8 architectures.  ... 
doi:10.1145/3195970.3196050 dblp:conf/dac/RosaBRO18 fatcat:t46jlv5y6jc43jkjjv63ucgjna

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Joel Criado, Marta Garcia-Gasulla, Pramod Kumbhar, Omar Awile, Ioannis Magkanaris, Filippo Mantovani
2020 2020 IEEE International Conference on Cluster Computing (CLUSTER)  
[3] for simulations at the molecular level.  ...  In this paper, we present our efforts to analyze the performance of CoreNEURON [4], a compute engine of widely used NEURON simulator.  ...  Figure 8 shows the energy spent in one simulation using a single node, respectively, powered by x86 Intel Skylake and Armv8 Marvell ThunderX2 CPUs.  ... 
doi:10.1109/cluster49012.2020.00077 dblp:conf/cluster/CriadoGAMM20 fatcat:yqzca6mwtje6tg6jpxputxlpni

A Dwarf-based Scalable Big Data Benchmarking Methodology [article]

Wanling Gao, Lei Wang, Jianfeng Zhan, Chunjie Luo, Daoyi Zheng, Zhen Jia, Biwei Xie, Chen Zheng, Qiang Yang, Haibin Wang
2017 arXiv   pre-print
90 percentage on both X86 64 and ARMv8 processors.  ...  For the purpose of architecture simulation, we construct and tune big data proxy benchmarks using the directed acyclic graph (DAG)-like combinations of the dwarf components with different weights to mimic  ...  Finally we construct the big data proxy benchmarks, which reduces simulation time and guarantees performance data accuracy for micro-architectural simulation.  ... 
arXiv:1711.03229v1 fatcat:t6vgjqxomrhbdju225pfc5yreu

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V [article]

Christopher Celio, Palmer Dabbelt, David A. Patterson, Krste Asanović
2016 arXiv   pre-print
We begin by comparing the dynamic instruction counts and dynamic instruction bytes fetched for the popular proprietary ARMv7, ARMv8, IA-32, and x86-64 Instruction Set Architectures (ISAs) against the free  ...  However, we observe that on SPEC CINT2006 RV64G executes on average 16% more instructions than x86-64, 3% more instructions than IA-32, 9% more instructions than ARMv8, but 4% fewer instructions than ARMv7  ...  We then modified the QEMU ARMv8 ISA simulator to count these instructions that are likely candidates for generating multiple micro-ops.  ... 
arXiv:1607.02318v1 fatcat:dhvyj5cjdfadjl3arwdnnqtv4u

TrABin: Trustworthy analyses of binaries

Andreas Lindner, Roberto Guanciale, Roberto Metere
2019 Science of Computer Programming  
Then, we implement two proof-producing transpilers, which respectively translate ARMv8 and CortexM0 programs to the intermediate language and generate a certificate.  ...  The usage of these platforms to verify software introduces the need for trusting both the correctness of the translation from binary code to intermediate language (called transpilation) and the correctness  ...  This work has been supported by the TrustFull project financed by the Swedish Foundation for Strategic Research and by the KTH CERCES Center for Resilient Critical Infrastructures financed by the Swedish  ... 
doi:10.1016/j.scico.2019.01.001 fatcat:2d7kc2q3tzdpxi3stirbwzk3pe

Efficiency Modeling and Analysis of 64-bit ARM Clusters for HPC

Joel Wanza Weloli, Sebastien Bilavarn, Said Derradji, Cecile Belleudy, Sylvie Lesmanne
2016 2016 Euromicro Conference on Digital System Design (DSD)  
This paper investigates the use of ARM 64-bit cores to improve the processing efficiency of upcoming HPC systems.  ...  It describes a set of available tools, models and platforms, and their combination in an efficient methodology for the design space exploration of large manycore computing clusters.  ...  ACKNOWLEDGMENT This work is supported partly by the H2020 Mont-Blanc project and a French ANRT CIFRE partnership between Bull atos technologies and LEAT (University of Nice Sophia Antipolis, CNRS).  ... 
doi:10.1109/dsd.2016.74 dblp:conf/dsd/WeloliBDBL16 fatcat:ogq5wpf5ijfojlah7wjjnw25wm

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, David Atienza, Katzalin Olcoz
2019 2019 Spring Simulation Conference (SpringSim)  
In this paper, we present gem5-X, a gem5-based system level simulation framework, and a methodology to optimize many-core systems for performance and power.  ...  Fast architectural exploration has become a key enabler in the proposal of architectural innovation.  ...  ACKNOWLEDGMENTS This work has been partially supported by the EC H2020 RECIPE (GA No. 801137) project, the ERC Consolidator Grant COMPUSAPIEN (GA No. 725657), the EU FEDER and the Spanish MINECO (GA No  ... 
doi:10.23919/springsim.2019.8732862 dblp:conf/springsim/QureshiSZAO19 fatcat:qd64dj453nb6flj6h3ve4sygwy

A high assurance virtualization platform for ARMv8

Christoph Baumann, Mats Naslund, Christian Gehrmann, Oliver Schwarz, Hans Thorsen
2016 2016 European Conference on Networks and Communications (EuCNC)  
Abstract-This paper presents the first results from the ongoing research project HASPOC, developing a high assurance virtualization platform for the ARMv8 CPU architecture.  ...  OSs) running on the platform.  ...  Parts of the verification work are supported by a framework grant from the Swedish Foundation for Strategic Research.  ... 
doi:10.1109/eucnc.2016.7561034 dblp:conf/eucnc/BaumannNGST16 fatcat:ntvwca4gefb4tbreqetcyxuj5u

Initial explorations of ARM processors for scientific computing

David Abdurachmanov, Peter Elmer, Giulio Eulisse, Shahzad Muzaffar
2014 Journal of Physics, Conference Series  
Over the course of next decade it is expected that flops/watt will be a major driver for the evolution of computer architecture.  ...  We present the results of our initial investigations into the use of ARM processors for scientific computing applications.  ...  Each port usually flags or flushes out some number of problems both in the generality of the build system and in the software itself. • Use an ARMv7/32bit port as a stepping stone to an ARMv8/64bit, hopefully  ... 
doi:10.1088/1742-6596/523/1/012009 fatcat:i56v6uagvjdrfeyygs72fttary

Cache Where you Want! Reconciling Predictability and Coherent Caching [article]

Ayoosh Bansal, Jayati Singh, Yifan Hao, Jen-Yang Wen, Renato Mancuso,, Marco Caccamo
2019 arXiv   pre-print
We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator.  ...  Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers.  ...  Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the NSF.  ... 
arXiv:1909.05349v1 fatcat:j3uly3xdv5fdzdeo2afh2xuglu

Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models [chapter]

Alasdair Armstrong, Brian Campbell, Ben Simner, Christopher Pulte, Peter Sewell
2021 Lecture Notes in Computer Science  
AbstractArchitecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification.  ...  We demonstrate this for the Armv8-A instruction-fetch model and self-modifying code examples of Simner et al.  ...  The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S  ... 
doi:10.1007/978-3-030-81685-8_14 fatcat:2oszlsec2fhabdxbnf6lh72lk4

Fast Execute-Only Memory for Embedded Systems [article]

Zhuojia Shen, Komail Dharsee, John Criswell
2020 arXiv   pre-print
We present PicoXOM: a fast and novel XOM system for ARMv7-M and ARMv8-M devices which leverages ARM's Data Watchpoint and Tracing unit along with the processor's simplified memory protection hardware.  ...  ACKNOWLEDGEMENTS We thank the anonymous reviewers for their insightful comments. This work was funded by ONR Award N00014-17-1-2996.  ...  PinLock simulates a smart lock reading user input from a serial port and deciding whether to unlock (send an I/O signal) based on whether the SHA-256 hashed input matches a precomputed hash.  ... 
arXiv:2006.00076v3 fatcat:cd6h22o4m5glnnp36465tx3z2y

TrustZone Explained: Architectural Features and Use Cases

Bernard Ngabonziza, Daniel Martin, Anna Bailey, Haehyun Cho, Sarah Martin
2016 2016 IEEE 2nd International Conference on Collaboration and Internet Computing (CIC)  
Then, we will review how TrustZone is implemented in the hardware and software of ARM products.  ...  We will also compare TrustZone with other implementations of trusted execution environments on the market.  ...  In ARMLock, the kernel is trusted. TrustZone is also used to simulate virtualization techniques. Pinto et al.  ... 
doi:10.1109/cic.2016.065 dblp:conf/coinco/NgabonzizaMBCM16 fatcat:w5nl3y3mdnanxn6hu76ykyli3q
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