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RP-SYN: synthesis of random pattern testable circuits with test point insertion

N.A. Touba, E.J. McCluskey
1999 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
testing, random pattern testability, test points.  ...  RP-SYN identifies random-pattern-resistant faults and eliminates them through testability-driven factoring combined with test point insertion.  ...  preserving random pattern testability preserving test-set preserving.  ... 
doi:10.1109/43.775638 fatcat:svkhd3wlt5hktbp46ujlawancu

A design for testability scheme with applications to data path synthesis

Scott Chiu, Christos A. Papachristou
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
Based on these two measures, a procedure of tradingoff between testing time and test hardware overhead is demonstrated.  ...  The basis of this work is a system level testability model. To quantify the qualitative description of testability, a controllability measure and an observability measure is developed.  ...  Figure 1 : 1 Basic Model for Testability Trade-offs If the output patterns of module A, produced by feeding A with random patterns generated by R1, are "random", then R2 need not be a controllable point  ... 
doi:10.1145/127601.127679 dblp:conf/dac/ChiuP91 fatcat:y2oi4ziyxrdjpdlnvn2x6fcmdi

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops

Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie
2012 IEEE transactions on computers  
Four types of new control point structures are introduced based on the logic cone analysis results to avoid degrading the testability.  ...  This paper presents a novel test point insertion method for pseudorandom built-in self-test (BIST) to reduce the area overhead.  ...  Since OR1200 and NOC designs are found to be relatively random pattern testable circuits, 2,048 and 16,000 random test patterns are applied.  ... 
doi:10.1109/tc.2011.189 fatcat:hxpmdyehazez7llddiysaetumy

Test point insertion using functional flip-flops to drive control points

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
2009 2009 International Test Conference  
Reconvergence is also checked to avoid degrading the testability.  ...  However, the proposed method uses functional flip-flops to drive control test points instead of test-dedicated flip-flops.  ...  Since the OR1200 and NOC designs are found to be relatively random pattern testable circuits, 2048 random test patterns are applied and the coverage is shown.  ... 
doi:10.1109/test.2009.5355688 dblp:conf/itc/YangNT09 fatcat:w5jogyfzzvgvtmqsjxb5mlfsme

Efficient test-point selection for scan-based BIST

Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, S. Bhawmik
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The proposed algorithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate.  ...  Under a pseudorandom BIST scheme, the objectives are 1) achieving a high random pattern fault coverage, 2) reducing the computational complexity, and 3) minimizing the performance as well as the area overheads  ...  For example, using weighted random patterns or embedding deterministic test patterns into the pattern generator has been shown to be helpful for detecting random pattern resistant faults [1] - [5] .  ... 
doi:10.1109/92.736140 fatcat:bh354hwvxnh2jhlivpax62tzjm

Quality Driven Manufacturing and SOC Designs

Srikanth Venkataraman, Nagesh Nagapalli, Lech Jozwiak
2007 8th International Symposium on Quality Electronic Design (ISQED'07)  
different features can be fed back to design and DFM tools.Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation  ...  , debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test are covered.  ...  patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield  ... 
doi:10.1109/isqed.2007.131 dblp:conf/isqed/VenkataramanNJ07 fatcat:hz74wl2rjjhuvjmhj4ozpbszfq

A hybrid algorithm for test point selection for scan-based BIST

Huan-Chih Tsai, Chih-Jen Lin, Sudipta Bhawmik, Kwang-Ting Cheng
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
With an event-driven mechanism, it can quickly identify a set of nodes whose testability need to be recalculated due to a test point, and then use gradients to estimate the impact of the rest of the circuit  ...  We present the results to illustrate that high fault coverages for both area-and timing-driven test point insertions can be obtained with a small number of test points.  ...  Introduction Because of the relatively low hardware overhead and the simplicity of test pattern generation, pseudo-random testing is a favorable technique for BIST.  ... 
doi:10.1145/266021.266205 dblp:conf/dac/TsaiCLB97 fatcat:tikmxk3ms5h2zi5daexhu7uha4

Built-in self-test support in the IBM Engineering Design System

B. L. Keller, T. J. Snethen
1990 IBM Journal of Research and Development  
To evaluate the effectiveness of built-in self-test (BIST) for logic circuits, the test design automation (TDA) group within the IBM Engineering Design System (EDS) has developed tools to support BIST.  ...  Some designs are inherently random-pattern testable, while others are random-pattern resistant.  ...  TARP Testability Analysis for Random Patterns. The TARP controller provides a single user interface to several random-pattern-testability analysis tools.  ... 
doi:10.1147/rd.342.0406 fatcat:4u4kq2buxbel3jtyaidil6j7t4

Testability Synthesis for Jumping Carry Adders

Chien-In Henry Chen, Mahesh Wagh
2002 VLSI design (Print)  
The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed  ...  Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy.  ...  Random test generation is done using parallel fault simulation. After the random patterns have been simulated, the algorithm performs a deterministic search to find tests for the remaining faults.  ... 
doi:10.1080/10655140290010079 fatcat:pjohywqzh5b3dcqo5j3xslh6mi

POWERTEST: a tool for energy conscious weighted random pattern testing

Xiaodong Zhang, K. Roy, S. Bhawmik
1999 Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)  
With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test BIST applications.  ...  Results on ISCAS benchmark circuits show that energy reduction of up to 97.82 can be achieved compared to equi-probable random-pattern testing with identical fault coverage while achieving high fault coverage  ...  Now let us consider stuck-at fault testability using random patterns.  ... 
doi:10.1109/icvd.1999.745191 dblp:conf/vlsid/ZhangRB99 fatcat:2gc6wdr6bfcytjg2seeavi7ryu

Linear Feedback Shift Register-Based Test Pattern Generators: A Comparative Study

Parangat Mittal, Daksh Shah
2020 Zenodo  
Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern Generators for testing of digital circuits in a BIST system.  ...  It is thus essential to design an efficient test pattern generator which utilizes least hardware, dissipates lowest power and generates most random sequence.  ...  The Test Pattern Generator (TPG) produces test patterns that are applied as inputs to the CUT.  ... 
doi:10.5281/zenodo.5039921 fatcat:6bt2er4mtfebvdmblvcd6l2zo4

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

I. Pomeranz, S.M. Reddy
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The random pattern testability for stuck-at faults remains unchanged.  ...  Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability.  ...  The random pattern testability of the circuits to stuck-at faults remained unchanged.  ... 
doi:10.1109/92.953501 fatcat:i4zn5yllezbezjnskhgjnvx2xm

The state of VLSI testing

L.M. Patnaik, H.S. Jamadagni, V.K. Agrawal, B.K.S.V.L. Varaprasad
2002 IEEE potentials  
Autonomous circuits such as LFSRs are used as low-cost test pattern generators for circuits testable by pseudo-random patterns.  ...  Random test generation (RTG) is a simple process that involves only the generation of random vectors. However, to achieve a high-quality test we need a large set of random vectors.  ... 
doi:10.1109/mp.2002.1033655 fatcat:krldasdnuvezxckc4zskltvs74

Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops

Joon-Sung Yang, Nur A. Touba
2014 ETRI Journal  
This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST ) to reduce the area overhead.  ...  Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flipflops.  ...  The test pattern generator automatically generates the patterns for application to the inputs of the circuit under test (CUT).  ... 
doi:10.4218/etrij.14.0113.1121 fatcat:dbtdeziyozfkfpib64g4yxbllu

The Weighted Random Test-Pattern Generator

H.D. Schnurmann, E. Lindbloom, R.G. Carpenter
1975 IEEE transactions on computers  
Irndex Terms-Fault-detecting patterns, heuristic algorithm, large-scale integration, testing, testing algorithms, test-pattern generator, weighted random patterns.  ...  The Weighted Random Test-Pattern Generator H. DANIEL SCHNURMANN, MEMBER, IEEE, ERIC LINDBLOOM, AND ROBERT G.  ... 
doi:10.1109/t-c.1975.224290 fatcat:47iju6irsff7rl2db6bb64sl4e
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