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Test vector chains for increased targeted and untargeted fault coverage

Irith Pomeranz, Sudhakar M. Reddy
2008 2008 Asia and South Pacific Design Automation Conference  
We demonstrate that a test set T 0 has a significant number of test vector chains that are effective in increasing the numbers of detections of target faults, i.e., faults targeted during the generation  ...  We introduce the concept of test vector chains, which allows us to obtain new test vectors from existing ones through single-bit changes without any test generation effort.  ...  We show the number of pairs in P , the number of test vectors in T chains , the minimum number of detections of a stuck-at fault detected by T chains , and the fault coverage of T chains with respect to  ... 
doi:10.1109/aspdac.2008.4484034 dblp:conf/aspdac/PomeranzR08a fatcat:oah7wi5t25bbpofknhk6sacko4

Test Encoding for Extreme Response Compaction

Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich
2009 2009 14th IEEE European Test Symposium  
The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns.  ...  fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.  ...  ACKNOWLEDGEMENT This work has been funded by the DFG under contract WU 245/4-1.  ... 
doi:10.1109/ets.2009.22 dblp:conf/ets/KochteHEW09 fatcat:7nmqbrvgxzelhflueznzq65jii

Efficient techniques for transition testing

Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran
2005 ACM Transactions on Design Automation of Electronic Systems  
Empirical data suggests that both data volume and application time will increase dramatically for such transition testing.  ...  Scan-based transition tests are added to improve the detection of speed failures in sequential circuits.  ...  When the test chain length increases beyond 3, the difference between the actual number of transition faults detected by the chain and the sum of edge weights in the chain can increase.  ... 
doi:10.1145/1059876.1059880 fatcat:3dhyxyshhvcehf6lgrl3dpmidy

Power Problems in VLSI Circuit Testing [chapter]

Farhana Rashid, Vishwani D. Agrawal
2012 Lecture Notes in Computer Science  
monitor of transition density in the scan register.  ...  Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to reduce test length with higher fault coverage in scan-BIST circuits.  ...  Proper selection of the input probability can increase the efficiency of test vectors in detecting faults, resulting in reduced test time [10] .  ... 
doi:10.1007/978-3-642-31494-0_54 fatcat:bk6syczvbbcu7l3mznw7qmksje

Generation of Reduced Test Vectors for Multiple Stuck at Faults using Genetic Algorithm

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
test vector (pattern) generation for MSA faults in the limited interval of runtime which also covers the test pattern sets for single faults.  ...  As seen many of circuits have single and multiple faults, as known many research has been carried out to generate test pattern set that detect MSA faults, here the proposed ATPG method makes use of test  ...  the value is '1' then the test vector can detect number of faults.  ... 
doi:10.35940/ijitee.k1271.0981119 fatcat:bf6rusjptfefrfargmpkhactk4

Test Compaction of Logic Blocks by using Fault Identification Method
IJARCCE - Computer and Communication Engineering

R.Vishnu Vardhan, M. Sathiskumar
2015 IJARCCE  
The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable.  ...  Fault equivalence and fault dominance method are used to detect the fault with minimum time period.  ...  This method increases the fault identification and the total number of faults can be identified. This test compaction also comprises of two set of fault coverage.  ... 
doi:10.17148/ijarcce.2015.4391 fatcat:v7zrnyd44bbelpfpxe4fh6ldmu

Defect aware X-filling for low-power scan testing

S Balatsouka, V Tenentes, X Kavousianos, K Chakrabarty
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
The main drawback of these methods is that X-filling for low power leads to lower defect coverage than random-fill. We propose a unified low-power and defect-aware X-filling method for scan testing.  ...  At the same time, this approach provides high defect coverage, which approaches and in many cases is higher than that for random-fill, without increasing the pattern count.  ...  As P increases, the defect coverage of the test vectors increases but they consume more shift power. Thus, P offers a tradeoff between scan-in switching activity and defect coverage.  ... 
doi:10.1109/date.2010.5456928 dblp:conf/date/BalatsoukaTKC10 fatcat:z6givpmljvaklaf457dr52ytdy

Layout-aware scan chain synthesis for improved path delay fault coverage

P. Gupta, A.B. Kahng, I.I. Mandoiu, P. Sharma
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded  ...  Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops  ...  Maloney, Rubin Parekhji and Tom Williams for useful discussions and Stefanus Mantik for help in obtaining the testcases.  ... 
doi:10.1109/tcad.2005.850900 fatcat:4oi5kfo6j5ajdnqpr3fopf5qra

Layout-aware scan chain synthesis for improved path delay fault coverage

P. Gupta, A.B. Kahng, I. Mandoiu, P. Sharma
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded  ...  Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops  ...  Maloney, Rubin Parekhji and Tom Williams for useful discussions and Stefanus Mantik for help in obtaining the testcases.  ... 
doi:10.1109/iccad.2003.159761 fatcat:ktwina3mkfbbzna3i7tpgwqvxy

Fuzzy approach to multimedia faulty module replacement

Jin Ding, Xiaojun Wang, C. McCorkell
1999 Fifth Asia-Pacific Conference on ... and Fourth Optoelectronics and Communications Conference on Communications,  
After analyzing the natures of random and pseudorandom test sequences applied to a module under test, we obtain the aliasing fault coverage between the random and pseudo-random sequences.  ...  The activity probability features of intermittent faults in the module under test are discussed based on Markov chain fiodel.  ...  Fig. 1 shows the relationship of the aliasing fault coverage against the input vector numbers in the simplest case where p(x)=l and n=6.  ... 
doi:10.1109/apcc.1999.820438 fatcat:a52rizv5fzbtnawean2z2hohwa

Scan-Out Power Reduction for Logic BIST

Senling WANG, Yasuo SATO, Seiji KAJIHARA, Kohei MIYASE
2013 IEICE transactions on information and systems  
For deriving larger scan-out power reduction with less fault coverage loss and preventing hardware overhead increase, the FFs to be filled are selected in a predetermined ratio.  ...  Nearly 51% reduction of scan-out power and 57% reduction of peak scanout power are achieved with little fault coverage loss for 20% FFs selection, while hardware overhead is little that only 0.05%. key  ...  the number of fault detection chances.  ... 
doi:10.1587/transinf.e96.d.2012 fatcat:k6snudgq6fe2riajbwesgcwpee

An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

Xiaoding Chen, Michael S. Hsiao
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates  ...  the need for the "serial full-scan" mode which is inefficient for both the test time and test power.  ...  Test time and power can be saved if for most vectors, only a small partition of the scan chain needs to be active for fault detection.  ... 
doi:10.1109/tvlsi.2007.893657 fatcat:qevsm6ilwvfk7nkjm6puequsoy

On the testing quality of random and pseudo-random sequences for permanent and intermittent faults

Jin Ding, Yu-Liang Wu
1999 Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)  
The mathematical analysis and experimental results show that the quality of the pseudorandom testing is better than that of the random testing for the permanent and intermittent faults.  ...  In this paper, the natures of random and pseudo-random input sequences and their influence on permanent and intermittent fault detecting are analyzed.  ...  Acknowledgment This paper is partially supported by the Hong Kong RGC Earmarked Grant No. CUHK4163/97E.  ... 
doi:10.1109/aspdac.1999.760021 dblp:conf/aspdac/DingW99 fatcat:wb3ynjf5nzckrfzo2qzxs3tzuu

A highly regular multi-phase reseeding technique for scan-based BIST

E. Kalligeros, X. Kavousianos, D. Nikolos
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
Multiple cells of the LFSR are utilized as sources for feeding the scan chain in different test phases.  ...  A seed-selection algorithm is moreover presented that, taking advantage of the multi-phase architecture, manages to reduce the number of the required seeds for achieving complete (100 %) fault coverage  ...  detecting the easy faults and the maximum number of LFSR cells that will be selected to feed the scan chain for detecting the easy faults respectively.  ... 
doi:10.1145/764883.764885 fatcat:are7lydeozbhvg6bc7elyh4yoy

A highly regular multi-phase reseeding technique for scan-based BIST

E. Kalligeros, X. Kavousianos, D. Nikolos
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
Multiple cells of the LFSR are utilized as sources for feeding the scan chain in different test phases.  ...  A seed-selection algorithm is moreover presented that, taking advantage of the multi-phase architecture, manages to reduce the number of the required seeds for achieving complete (100 %) fault coverage  ...  detecting the easy faults and the maximum number of LFSR cells that will be selected to feed the scan chain for detecting the easy faults respectively.  ... 
doi:10.1145/764808.764885 dblp:conf/glvlsi/KalligerosKN03 fatcat:rhd5rqnvfbdltfmg3aswyjbkjq
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