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Test register insertion with minimum hardware cost

A.P. Stroele, H.-J. Wunderlich
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)  
An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs  ...  It is found that often CBILBOs lead to a minimum hardware overhead and also simplify test scheduling and test control.  ...  The minimum cost placement strongly depends on the hardware overheads associated with the built-in test cells: c B : cost of replacing a D-flip-flop by a BILBO cell c Bt : cost of inserting a transparent  ... 
doi:10.1109/iccad.1995.479998 dblp:conf/iccad/StroeleW95 fatcat:5hbjnu7l7zecjc642vitowmvha

Hardware-optimal test register insertion

A.P. Stroele, H.-J. Wunderlich
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs  ...  Hence, test scheduling is not required, test control is simplified, and test application time is reduced. Index Terms-BILBO, built-in self-test, CBILBO, test register insertion.  ...  Kiefer for assistance with the implementation and the experiments.  ... 
doi:10.1109/43.703833 fatcat:54p3ehmx3bd3xptx3g636gsgqq


Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri, Hideo Fujiwara
2016 Jurnal Teknologi  
with minimal cost when vertices are removed.  ...  The selection of MISR is performed by extended minimum feedback vertex set (MFVS) algorithm that identifies a set of vertices (representing test register) which breaks all the loops of extended R-graph  ...  Regarding the hardware cost, CBILBO is more expensive than BILBO and also inserting a transparent test register is more expensive than modifying an existing register with CBILBO.  ... 
doi:10.11113/jt.v79.8479 fatcat:gc263ro6mrek7llipcqt2gvdcq

Non-scan design for testable data paths using thru operation

Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
1997 Systems and Computers in Japan  
We dene a testable measure, weak testability, and consider the problem to make the data path weakly testable with minimum hardware overhead.  ...  Abstract| We present a new non-scan DFT technique for register-transfer (RT) level data paths.  ...  Experimental results show that our technique obtains high test eciency with low hardware overhead and that the weak testability cost has correlation with the test generation time.  ... 
doi:10.1002/(sici)1520-684x(199709)28:10<60::aid-scj7>;2-a fatcat:qezatwghnbedrjcipu2q4lbmiu

Analysis of data-leak hardware Trojans in AES cryptographic circuits

Trey Reece, William H. Robinson
2013 2013 IEEE International Conference on Technologies for Homeland Security (HST)  
Trojans Hardware Trojans Insertion Phase Abstraction Level Activation Effects Location Specification Design Fabrication Testing Assembly System Level Development Environ Register-transfer  ...  Is there a minimum cost? 6 S. T. King, J. Tucek, A. Cozzie, C. Grier, W. Jiang, and Y.  ... 
doi:10.1109/ths.2013.6699049 fatcat:fg5cbjt2dbeyvo52x7562kacsu

High-level synthesis of recoverable VLSI microarchitectures

D.M. Blough, F.J. Kurdahi, Seong Yong Ohm
1999 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The first uses a prioritized cost function in which functional unit (FU) cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of FU and register costs.  ...  Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented.  ...  The work of [14] attempts to insert recovery points to minimize execution time with given hardware resources, while the approach of [7] and [13] attempts to minimize hardware overhead with a given  ... 
doi:10.1109/92.805747 fatcat:pnpj76ehtzcehna3yutb4svm2q

Application-driven co-design of fault-tolerant industrial systems

F. Restrepo-Calle, A. Martinez-Alvarez, H. Guzman-Miranday, F. R. Palomoy, S. Cuenca-As
2010 2010 IEEE International Symposium on Industrial Electronics  
The proposal combines the flexibility and low cost of Software Implemented Hardware Fault Tolerance (SIHFT) techniques with the high reliability of selective hardware replication.  ...  Using the proposed methodology, the design was guided by the requirements of the application, leading us to explore several trade-offs among reliability, performance and cost.  ...  sector calzado' (GV/2009/098) (Generalitat Valenciana) and 'Aceleración hardware de algoritmos industriales para el sector calzado' (GRE08-P11) (University of Alicante).  ... 
doi:10.1109/isie.2010.5637483 fatcat:z4eavmlkonavvi5fbjggzi3odu

Efficient BIST hardware insertion with low test application time for synthesized data paths

Nicola Nicolici, Bashir M. Al-Hashimi
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis.  ...  The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST environment.  ...  The BIST hardware insertion algorithm looks for a testable solution with a primary goal of minimizing test application time and as a second order goal to minimize BIST hardware overhead.  ... 
doi:10.1145/307418.307507 fatcat:nt5k77yv4fcazktoibx5h2d4zu

A design-for-verification technique for functional pattern reduction

Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
2003 IEEE Design & Test of Computers  
hardware.  ...  Some limitations become unnecessary in functional verification because the designs under test are not real hardware.  ... 
doi:10.1109/mdt.2003.1188262 fatcat:j75zxkpmojd6lmeswj2ouofzta

High-level synthesis for testability

Kenneth D. Wagner, Sujit Dey
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate easily testable implementations.  ...  A testability cost function is used to evaluate the costs associated with each type of loop formed and the scan registers necessary to break the loops.  ...  Subsequently, a pair with the smallest cost is selected.  ... 
doi:10.1145/240518.240543 dblp:conf/dac/WagnerD96 fatcat:fj4kn2fit5aw5kyyufgwjcq6rm

Idetic: A high-level synthesis approach for enabling long computations on transiently-powered ASICs

A. Mirhoseini, E. M. Songhori, F. Koushanfar
2013 2013 IEEE International Conference on Pervasive Computing and Communications (PerCom)  
We define an objective function that aims to find the checkpoints which incur minimum overhead and minimize recomputation energy cost.  ...  We address the power transiency and unpredictability problem by optimally inserting checkpoints.  ...  The minimum OF cost for inserting the k th checkpoint at t, includes the cost of checkpointing at that point (Line 8) plus the minimum overall energy that is consumed before the t th state (Line 9).  ... 
doi:10.1109/percom.2013.6526735 dblp:conf/percom/MirhoseiniSK13 fatcat:3pbi7vtunbe47bwarde46xxmty

Reconfiguration-Based VLSI Design for Security

Bao Liu, Brandon Wang
2015 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
degradation; we further prevent a hardware Trojan from gaining unauthorized memory access at cost of 4.42% area increase, negligible power consumption increase, and 11.30% critical path delay increase  ...  In our case studies based on a SPARC V8 LEON2 processor, we prevent software-or hardware-based code injection attacks at cost of 0.72% area increase, negligible power consumption increase and no performance  ...  system at minimum cost.  ... 
doi:10.1109/jetcas.2014.2372431 fatcat:v2rsd2c2rjacbd2y7vfn7unwt4

Reducing Context Switch Overhead with Compiler-Assisted Threading

Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö
2008 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing  
The test input data used was the longest MP3 file in the DENbench suite (music128stereo), a 60 s sample with 44100 Hz sampling frequency.  ...  Many modern processors have large register banks, and the cost of saving the state can be substantial.  ... 
doi:10.1109/euc.2008.181 dblp:conf/euc/JaaskelainenKTKL08 fatcat:7m3oq27ll5hkxplfsdgmotu7eu

FPGA Based Efficient LFSR Architecture for Verification Using Optimized BIST Technique

2020 International Journal of Emerging Trends in Engineering Research  
The modified LFSR has been designed with minimum XOR gates and clock gating circuit which improves the performance of the system.  ...  Built InSelf Test (BIST) is generally used to verify the correctness of the design in real time at hardware level.  ...  Here the Pseudo Random Sequence Generator (PRSG) architecture is modified with minimum gates with clock gating circuit.  ... 
doi:10.30534/ijeter/2020/1468102020 fatcat:b3gcof557nbzvi3e4ss35sh5cy

Transparent In-Circuit Assertions for FPGAs

Eddie Hung, Tim Todman, Wayne Luk
2017 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above 200MHz, at the cost of a small power penalty.  ...  We use network-flow techniques to route necessary signals to assertions via spare flipflops, eliminating any performance degradation, even on large designs (92% of slices in one test).  ...  Step 3 applies minimum-cost flow techniques to transport user signals (perhaps distributed across the whole device) needed by the assertion circuit into its vicinity, via pipelining registers.  ... 
doi:10.1109/tcad.2016.2618862 fatcat:ooiannchh5girmykvmrqu754e4
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