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A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits
2011
International Journal of VLSI Design & Communication Systems
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This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal-Oxide-Semiconductor (CMOS) analog integrated circuits (ICs) interconnects ...
When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. ...
CONCLUSION This paper has presented a novel test methodology based on a fault dictionary for the detection of open circuit faults occurring in CMOS analog circuits. ...
doi:10.5121/vlsic.2011.2301
fatcat:aqs4yq3nz5gshgoetwg3jtfxky
Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families
2000
IEEE transactions on circuits and systems - 2, Analog and digital signal processing
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Index Terms-Concurrent testing, delay fault and stuck open fault testing, design for testability, fully testable CMOS circuit, VLSI testing. . ...
It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: 1) faults which cause delayed transitions at the output node due to some open defects and ...
Miller, Dean of Engineering at the University of Victoria, Canada, for his constructive and valuable comments. ...
doi:10.1109/82.885134
fatcat:erlhh6kkmbaanlvljxhhhsgtki
Guest editors' introduction: defect-oriented testing in the deep-submicron era
2002
IEEE Design & Test of Computers
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Defect-oriented test strategies first analyze defect properties, and then determine the best test technique for detection. ...
The miniaturization laws in this domain generated a new scaling approach-constant field scaling-as an alter-7 ...
Traditional defect-oriented test methods have mainly targeted detection of bridges because this defect mechanism was considered the most probable in previous CMOS generations. ...
doi:10.1109/mdt.2002.1033786
fatcat:pypu7pvts5hexkoo7bsfjy4zbq
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits
1994
VLSI design (Print)
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It is shown that logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). ...
It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. ...
TEST CIRCUITS The general structure of the test circuit used in the fault analysis is shown in Figure 4 . ...
doi:10.1155/1994/70696
fatcat:5om3folpn5addjdewonsfxhd5a
Impact of gate tunnelling leakage on CMOS circuits with full open defects
2007
Electronics Letters
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Interconnecting lines with full open defects become floating lines. ...
In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. ...
Introduction: Open defects are among the most abundant defects in CMOS circuits. An interconnecting open defect consists of the partial or total breaking of a line. ...
doi:10.1049/el:20072117
fatcat:vvquww6exjduthahijjdegpmpm
CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture
2017
Journal Electrical and Electronic Engineering
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Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. ...
Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. ...
Testing with Stuck at 0 Fault Stuck at 0 is a basic fault model for testing performance of any design. In such cases, particular elements are set to be open. ...
doi:10.11648/j.jeee.20170506.15
fatcat:z4csd24gtzh55arj4wcjemesaq
Author index
2013
2013 14th Latin American Test Workshop - LATW
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Defect Detection in Nanometer CMOS Circuits using Low VDD and Body Bias � Vishwani AGRAWAL • A Test Time Theorem and Its Applications � Walter LANCIONI Low-Cost DC BIST for Analog Circuits: A Case Study ...
Oscillator for Open Loop Modulation of Low Cost, Low Power RF Transceiver � Hector VILLACORTA Bridge Defect Detection in Nanometer CMOS Circuits using Low VDD and Body Bias � Heinrich Theodor VIERHAUS ...
doi:10.1109/latw.2013.6562652
fatcat:oj5reuna4rgn5ekbpnxr2zjyje
Test generation for resistive opens in CMOS
2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02
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We develop a test generation methodology for this fault model which enables generation of test vectors that test a percentage of the longest sensitizable paths in the design and also test each net for ...
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. ...
This research effort was supported by the Semiconductor Research Corporation through contract 99-TJ-715
ACKNOWLEDGEMENTS We would like to thank Rathish Jayabharathi for the helpful discussions and useful ...
doi:10.1145/505318.505321
fatcat:jhh5xts2vna4hgdmbpxx3gvl74
Test generation for resistive opens in CMOS
2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02
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We develop a test generation methodology for this fault model which enables generation of test vectors that test a percentage of the longest sensitizable paths in the design and also test each net for ...
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. ...
This research effort was supported by the Semiconductor Research Corporation through contract 99-TJ-715
ACKNOWLEDGEMENTS We would like to thank Rathish Jayabharathi for the helpful discussions and useful ...
doi:10.1145/505306.505321
dblp:conf/glvlsi/KrishnamacharyA02
fatcat:npopq64hfffxjpycw3upxy2j3e
On Defect Oriented Testing for Hybrid CMOS/Memristor Memory
2011
2011 Asian Test Symposium
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Second, a simulation model for defect injection and circuit simulation is proposed. ...
However, research on defect analysis for yield and quality improvement is still in its infancy stage. ...
Defects in CMOS-to-nano vias (CNVs) Defects in CNVs can be either opens or bridges. ...
doi:10.1109/ats.2011.66
dblp:conf/ats/HaronHH11
fatcat:glz36dv5svdmtbw33w6a3jz6yi
Fine-Grained Defect Diagnosis for CMOL FPGA Circuits
2020
IEEE Access
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In general, as the defect rate is low in CMOS circuits, a single fault is assumed for efficient test and diagnosis. ...
In this section, methods for generating circuit configurations that improve the quality of test and diagnosis are proposed. ...
doi:10.1109/access.2020.3022027
fatcat:l6fdv3sva5c4xpoqbfwshmsuzm
Assessment on the Adequacy of Current Supply Testing Methods in CMOS Operational Amplifier
2020
International Journal of Engineering and Advanced Technology
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We will assess the viability of current checking systems in distinguishing Bridge and open deformities in CMOS operational amplifiers. ...
This paper proposes examination on the adequacy of current gracefully testing strategies in cmos operational amplifiers. ...
Most of the studies were done on advanced CMOS circuits and just a bunch of examinations have been accounted for on simple CMOS circuits.
II. ...
doi:10.35940/ijeat.e9313.069520
fatcat:ovpo6o53p5hjzpun7ija5f2bsq
A self-test and self-repair approach for analog integrated circuits
2012
2012 2nd Baltic Congress on Future Internet Communications
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in analog CMOS circuits during the manufacturing process. ...
With the continuous increase of integration densities and complexities, secure integrated circuits (ICs) are more and more required to guarantee reliability for safety-critical applications in the presence ...
ACKNOWLEDGMENT The research work presented in this paper is partially sponsored by Transcend Epoch International Co., Ltd, Belize and Hong Kong. ...
doi:10.1109/bcfic.2012.6217990
dblp:conf/bcfic/KarmaniKMKHR12
fatcat:px2gc6n4cbgb5ngf4cb6ve2maa
IDDQTesting Experiments for Various CMOS Logic Design Structures
1997
VLSI design (Print)
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This study was carded out by designing, simulating, fabricating, and testing CMOS devices with built-in defects. ...
The results show that IDDQtesting can detect some types of defects in precharge and pseudo-NMOS circuits but may require partitioning circuitry for the latter. ...
Acknowledgments This work was supported, in part, by IBM-Charlotte. ...
doi:10.1155/1997/51094
fatcat:2r7k4xynkbe3betpy4n6m3ekry
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC
2008
2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
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Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. ...
The test coverage (fault efficiency) can be increased by the new generator by up to 0.4 % in comparison to full stuck-at test. Layout analysis for a set of benchmarks has been performed. ...
In addition, the research provides for an insight to defect distribution in real CMOS layouts. ...
doi:10.1109/dsd.2008.98
dblp:conf/dsd/PleskaczJRRUK08
fatcat:zcyfy2k5hbeqhakcirsxzqhkqq
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