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Telegraphos: high-performance networking for parallel processing on workstation clusters

E.P. Markatos, M.G.H. Katevenis
Proceedings. Second International Symposium on High-Performance Computer Architecture  
Networks of workstations and high-performance microcomputers have been rarely used for running highperformance applications like multimedia, simulations, scientific and engineering applications, because  ...  In this paper we present Telegraphos, a distributed system that provides efficient shared-memory support on top of a workstation cluster.  ...  Papadourakis for implementing the rest of the Telegraphos I system prototype; G. Kornaros and N. Houstis for porting the Telegraphos I switch design to the Telegraphos II ASIC technology; and Ch.  ... 
doi:10.1109/hpca.1996.501181 dblp:conf/hpca/MarkatosK96 fatcat:g4ojnyqsgnedjoptgdrebiyeza

The remote enqueue operation on networks of workstations [chapter]

Evangelos P. Markatos, Manolis G. H. Katevenis, Penny Vatsolaki
1998 Lecture Notes in Computer Science  
Modern networks of workstations connected by Gigabit networks have the ability to run high-performance computing applications at a reasonable performance, but at a signi cantly lower cost.  ...  In this paper we describe a new operation, the remote-enqueue atomic operation, which can be used in multiprocessors, and workstation clusters.  ...  Acknowledgments This work was supported in part by ESPRIT project 6253 \Supercomputer Highly Parallel System" (SHIPS), funded by the European Union, through DG  ... 
doi:10.1007/bfb0052203 fatcat:475a7zrstjadzc7j25m4x4lp5u

Switcherland

Hans Eberle, Erwin Oertli
1998 SIGARCH Computer Architecture News  
We present Switcherland, a scalable communication architecture based on crossbar switches that provides QoS guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission  ...  by also covering the end nodes of the network, (iii) it provides low latency in the order of one microsecond per switch, and (iv) it uses a communication model based on a global memory to simplify programming  ...  Thomas Gross made many helpful comments on an earlier draft of this paper.  ... 
doi:10.1145/279361.279373 fatcat:rl4ky7aghjajvlgb52k43bzzl4

Pipelined memory shared buffer for VLSI switches

Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
1995 Computer communication review  
It is simpler and smaller than wide or interleaved org anizations, and it is particularly suitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion.  ...  Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is not more  ...  Papadourakis for implementing the rest of the Telegraphos I system prototype; G. Kornaros and N. Houstis for porting the Telegraphos I switch design to the Telegraphos II ASIC technology; and Ch.  ... 
doi:10.1145/217391.217406 fatcat:plaroihvtrdv5diyokecnpcz54

Pipelined memory shared buffer for VLSI switches

Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
1995 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication - SIGCOMM '95  
It is simpler and smaller than wide or interleaved org anizations, and it is particularly suitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion.  ...  Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is not more  ...  Papadourakis for implementing the rest of the Telegraphos I system prototype; G. Kornaros and N. Houstis for porting the Telegraphos I switch design to the Telegraphos II ASIC technology; and Ch.  ... 
doi:10.1145/217382.217406 dblp:conf/sigcomm/KatevenisVE95 fatcat:ezwb2b642zhy7d5o3m3nhdavw4

Operating system support for high-speed communication

Peter Druschel
1996 Communications of the ACM  
For example, parallel programming systems implemented on workstation clusters are very communication-intensive.  ...  For example, a parallel programming system implemented on a workstation cluster can gain efficiency by using specialized message-passing protocols and buffering strategies instead of generic TCP/IP network  ...  To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission and/or a fee.  ... 
doi:10.1145/234215.234470 fatcat:2vtjmwg3sbakxbmq3vvtlhb3zu

Switcherland: a QoS communication architecture for workstation clusters

H. Eberle, E. Oertli
Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235)  
We present Switcherland, a scalable communication architecture based on crossbar switches that provides QoS guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission  ...  by also covering the end nodes of the network, (iii) it provides low latency in the order of one microsecond per switch, and (iv) it uses a communication model based on a global memory to simplify programming  ...  Thomas Gross made many helpful comments on an earlier draft of this paper.  ... 
doi:10.1109/isca.1998.694766 dblp:conf/isca/EberleO98 fatcat:cbcwuw3lznbqnf2fvivykihdmu

User-level DMA without operating system kernel modification

E.P. Markatos, M.G.H. Katevenis
Proceedings Third International Symposium on High-Performance Computer Architecture  
Soon, the operating system overhead associated with starting a DMA will be l a r ger than the data transfer itself, esp. for small data transfers.  ...  DMA operations are t r aditionally initiated b y t h e operating system kernel, mainly to prevent one application from tampering with another applications' data.  ...  The HIC technology addresses in particular the marketplace for parallel systems interconnect and provides a major enabling technology for the Open Microprocessor systems Initiative.  ... 
doi:10.1109/hpca.1997.569696 dblp:conf/hpca/MarkatosK97 fatcat:abagvxa7yna4hflxyp7tksezgu

Address translation mechanisms in network interfaces

I. Schoinas, M.D. Hill
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture  
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host.  ...  We classify NI address translation implementations based on where the lookup and the miss handling are performed (CPU or NI).  ...  Many thanks to Rich Martin, David Culler and the NOW group at University of California for releasing the AM communication package for Myrinet, which provided the infrastructure for Blizzard's messaging  ... 
doi:10.1109/hpca.1998.650561 dblp:conf/hpca/SchoinasH98 fatcat:5skqlqifpnd7rhzcq23r7omzgq