1 Hit in 6.6 sec

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

Mu-Tien Chang, P. Rosenfeld, Shih-Lien Lu, B. Jacob
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
We optimize SRAM for low leakage and optimize STT-RAM for low write energy.  ...  Each of these technologies has inherent weaknesses: SRAM is relatively low density and has high leakage current; STT-RAM has high write latency and write energy consumption; and eDRAM requires refresh  ...  Acknowledgments The authors would like to thank Professor Sudhanva Gurumurthi and the reviewers for their valuable inputs.  ... 
doi:10.1109/hpca.2013.6522314 dblp:conf/hpca/ChangRLJ13 fatcat:65gnxhvysbg4ngg24hgx7uv2ve