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1991 Applications of Learning and Planning Methods  
Despite successes, the state of the art in logic synthesis is limited in terms of range and quality.  ...  Recent efforts in VLSI design synthesis (logic synthesis) have shown how heuristic techniques can generate human-quality hardware designs in a fraction of man ual design time.  ...  Synthesis in the VLSI domain is called logic synthesis.  ... 
doi:10.1142/9789812812414_0006 fatcat:audctk4uxbflvormes7lldjoru

Design-for-adaptivity of microarchitectures

Maxim Rykunov, Andrey Mokhov, Danil Sokolov, Alex Yakovlev, Albert Koelmans
2013 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors  
reshape for needed instruction set or operating mode.  Synthesis results: * Top-level control -326 gates * ALU control -220 gates  ASIC implementation of Asynchronous Intel 8051 microprocessor in 130nm  ...  Synthesis of processor instruction sets from high-level ISA specifications.  ...   Synthesis results: * Top-level control -326 gates * ALU control -220 gates Microprocessor Technology MIPS Average Power, mW MIPS/W Energy per instr., pJ S80C51 3.3V,350nm 4 40  ... 
doi:10.1109/asap.2013.6567596 dblp:conf/asap/RykunovMSYK13 fatcat:osn23jtwinb37mkolycypoufl4

Page 922 of Automation and Remote Control Vol. 35, Issue 6 [page]

1974 Automation and Remote Control  
AN ADAPTIVE METHOD FOR LOGICAL-CIRCUIT SYNTHESIS W,.  ...  Alliger This paper deals with an adaptive approach to the synthesis of logical circuits which are widely ap- plied in various automatic systems, In recent years adaptive methods have been widely applied  ... 

A Choreography-Based and Collaborative Road Mobility System for L'Aquila City

Marco Autili, Amleto Di Salle, Francesco Gallo, Claudio Pompilio, Massimo Tivoli
2019 Future Internet  
Next Generation Internet (NGI) is the European initiative launched to identify the future internet technologies, designed to serve the needs of the digitalized society while ensuring privacy, trust, decentralization  ...  Adaptation logic Starting from an adapter model the adaptation logic is automatically generated into a set of ADs The adaptation logic to bind the concrete services to the choreography participants in  ...  Dev3 was assigned to the coordination logic in the experimental unit 2. Finally, Dev4 was assigned to the prosumer services and the adaptation logic in the same experimental unit 2.  ... 
doi:10.3390/fi11060132 fatcat:5kw2ygn45nbalagkejvwp5l7oq

High-Level Synthesis of Digital Circuits [chapter]

Giovanni De Micheli
1993 Advances in Computers  
In general, logic synthesis systems provide two capabilities: technology-independent circuit optimization and technology mapping into library part~.~ Most available systems have been conceived for combinational  ...  The future looks promising for this technology, however. I expect high-level synthesis techniques to mature rapidly-just as logic synthesis has done in the last decade-and to be widely used.  ... 
doi:10.1016/s0065-2458(08)60406-4 fatcat:miay4gf7y5hrnldx6tl2gz4m5i

CAD Optimization Technique in Reconfigurable Computing System using Hybrid Architecture

Sunil Kr. Singh, R. K. Singh, M. P. S. Bhatia
2011 International Journal of Computer Applications  
The two main types of programmable logic devices, fieldprogrammable gate arrays (FPGA) based on LUTs technology and complex programmable logic device (CPLD) based on PLAs technology.  ...  architecture-specific optimization, physical synthesis, RT-level and behaviour-level synthesis.  ...  Technology mapping and optimization which was previously called once is now called twice, once before adaptation and once after adaptation.  ... 
doi:10.5120/2935-3890 fatcat:trnoi6hhtbbi7lwejmsggf36da

Structural-Parametric Synthesis of an Adaptive Fuzzy-Logical System

Siddikov Isamiddin Xakimovich, Umurzakova Dilnoza Maxamadjonovna, Yadgarova Dilnoza Baxtiyarovna
2020 Universal Journal of Electrical and Electronic Engineering  
To correct the parameters and structure of the fuzzy-logical controller, an adaptation block is proposed in the control system loop.  ...  The proposed structural-parametric adaptation algorithm in the process control problems allows to reduce the number of iterations in the process of network training, to reduce the error in the calculation  ...  Recently, there has been an extremely high interest in one of the most important applications of the theory of fuzzy sets -the analysis and synthesis of fuzzy regulators and control systems for technological  ... 
doi:10.13189/ujeee.2020.070204 fatcat:b2afsck6jbfa7mgmlyfgv3ki3u

Panel and embedded tutorial — Logic synthesis and place and route: After 20 years of engagement, wedding in view?

M Casale-Rossi, A Domic
2011 2011 Design, Automation & Test in Europe  
, logic synthesis, placement, and routing algorithms reached a maturity level which enabled the birth of the first wave of modern EDA companies and design implementation tools: Silvar-Lisco, Cadence, Synopsys  ...  The first half of the 80's marked a fundamental milestone in the history of design implementation: an amazing number of key research papers were published, in a relatively short period of time; suddenly  ...  Synopsys' Dr Antun Domic, will moderate a panel of university and industry experts who will discuss what new links are needed between logic synthesis and place & route, and whether a closer -exclusive  ... 
doi:10.1109/date.2011.5763016 fatcat:zrf6sswnafh73dl6o3lu7l6hby

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis Targeting XOR-rich Circuits

Luca Amaru, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
To exploit this opportunity in logic synthesis for XOR-rich circuits, we developed a BBDD-based One-Pass Synthesis (OPS) methodology.  ...  Considering CMOS technology, the BBBD-based OPS reduces the device count by 31.5% on average compared to commercial synthesis tool.  ...  We proposed a new canonical BDD extension, the Biconditional BDD (BBDD), capable to efficiently support One-Pass Synthesis (OPS) for XOR-rich logic circuits.  ... 
doi:10.7873/date.2013.211 dblp:conf/date/AmaruGM13 fatcat:y2dcpzufsjgw5ayanvhn3cvefq

Adaptive FPGAs: High-Level Architecture and a Synthesis Method

Valavan Manohararajah, Stephen Brown, Zvonko Vranesic
2006 2006 International Conference on Field Programmable Logic and Applications  
We also describe a synthesis method that identifies and resynthesizes mutually exclusive pieces of logic so that they may share the resources available in an AFPGA.  ...  An AFPGA is adaptative in the sense that the functionality of subcircuits placed on the chip can change in response to changes observed on certain control signals.  ...  AFPGAS: CAD FLOW The CAD flow for AFPGAs is illustrated in Figure 7 . The first two steps, synthesis and technology mapping, are the same as in an FPGA CAD flow.  ... 
doi:10.1109/fpl.2006.311224 dblp:conf/fpl/ManohararajahBV06 fatcat:ykczs7avyve4xpkibkjqvfxgty

Reversible Logic Circuit Synthesis and Optimization Using Adaptive Genetic Algorithm

Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan
2015 Procedia Computer Science  
In this work, we proposed an Adaptive Genetic Algorithm (AGA) for synthesizing reversible logic circuits.  ...  Synthesis of reversible logic and generating reversible logic circuit automatically with lower cost always has been a challenging task as reducing the search space is one of the major issues in the synthesis  ...  Work by Landauer 2 showed that, regardless of the underlying technology, conventional logic circuits dissipate heat in an order of 2 kTLn joules for every bit of information that is lost, where k is  ... 
doi:10.1016/j.procs.2015.10.054 fatcat:53bp77ursze2nbtk2qedyzijsm

FPGA prototyping of a RISC processor core for embedded applications

M. Gschwind, V. Salapura, D. Maurer
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We show how hardware emulation based on programmable logic can be integrated into the hardware/software codesign flow.  ...  We show how to perform targeted optimizations to fully exploit the capabilities of the target technology while maintaining a common source base.  ...  Logic synthesis is targeted at FPGAs to exercise the design for verification purposes. Final implementation is performed using logic synthesis to an ASIC technology.  ... 
doi:10.1109/92.924027 fatcat:y2lgnrazwbfchixzfge7kpmbxu

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Andras Moritz
2009 Microelectronics Journal  
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology.  ...  In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics.  ...  Synthesis, structural transformations and yield projection Synthesis The resulting logic is then synthesized in the appropriate type of logic (PLA, LUT, and multi-level logic) as defined by the architectural  ... 
doi:10.1016/j.mejo.2008.07.072 fatcat:te4h6zgiincqfnngggutvziuia

Efficient arithmetic logic gates using double-gate silicon nanowire FETs

Luca Arnani, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)  
In this paper, we present a complete design framework of DG-SiNWFETs technology for arithmetic logic.  ...  Then, we study the application of these arithmetic gates in the automated synthesis of datapath circuits which are dominated by arithmetic operations.  ...  To fully harness the potential of DG-SiNWFETs during logic synthesis, we adapted a novel synthesis flow that natively supports the logic expressive power of controllable polarity devices.  ... 
doi:10.1109/newcas.2013.6573572 dblp:conf/newcas/ArnaniGM13 fatcat:7ojk2qv2pbc6nkgs5qodksv2ee

Technology mapping for large complex PLDs

Jason Helge Anderson, Stephen Dean Brown
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consist of a large number of PLA-style logic blocks.  ...  We describe an approach that allows existing multi-level synthesis techniques [13] to be adapted to produce circuits that are well-suited for implementation in CPLDs.  ...  Each in the figure represents a programmable switch. The block in the figure can be adapted to represent the logic blocks in most commercially-available CPLDs.  ... 
doi:10.1145/277044.277220 dblp:conf/dac/AndersonB98 fatcat:pj6cqzowencl5mw72lci4t6jwi
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