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Technology mapping for minimizing gate and routing area

A. Lu, G. Stenz, F.M. Johannes
Proceedings Design, Automation and Test in Europe  
This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout.  ...  The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals".  ...  Kurt Antreich at the Technical University of Munich for his continuous support to their work. Thanks also to Christian Legl, Klaus Eckl and Bernhard Rohfleisch for valuable discussions.  ... 
doi:10.1109/date.1998.655929 dblp:conf/date/LuSJ98 fatcat:ziv2auehmjfq7jnicae7qc7mxm

An exact solution to simultaneous technology mapping and linear placement problem

Jinan Lou, Salek, Pedram
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout  ...  The proposed algorithm relies on generation of gate-area versus cut-width curves using a dynamic programming approach.  ...  For example, technology mapping algorithms minimize gate area or delay without considering the interconnect structure and routing overhead of the resulting circuit.  ... 
doi:10.1109/iccad.1997.643610 dblp:conf/iccad/LouSP97 fatcat:wj7ixj6lgjej7atsze77dsmi4y

Understanding and addressing the impact of wiring congestion during technology mapping

Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In this paper we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the cost function [15] , and then applies incremental  ...  localized unmapping and remapping on congested areas.  ...  Acknowledgments The authors are grateful to Roberto De Checchi and Auro Lazzini, of Cadence Design Systems, Inc., Rozzano, Italy, for several enlightening discussions on physical design and continuous  ... 
doi:10.1145/505388.505421 dblp:conf/ispd/PandiniPS02 fatcat:kzouehxb65fvvfrumttodwzeie

Understanding and addressing the impact of wiring congestion during technology mapping

Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In this paper we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the cost function [15] , and then applies incremental  ...  localized unmapping and remapping on congested areas.  ...  Acknowledgments The authors are grateful to Roberto De Checchi and Auro Lazzini, of Cadence Design Systems, Inc., Rozzano, Italy, for several enlightening discussions on physical design and continuous  ... 
doi:10.1145/505418.505421 fatcat:hl7qj3mxe5abzient4jlyup6ge

Technology mapping with crosstalk noise avoidance

Fang-Yu Fan, Hung-Ming Chen, I-Min Liu
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
-Crosstalk map After placement and routing by a point model, construct crosstalk map for each fanin net on a match a point model-a center point (x,y) represents the location of gate pins and its  ...  with up to 4 strengths for each gate ISCAS'85 benchmarks Capo for pre-placement Placement and routing in Cadence's SoC Encounter Timing and noise analysis in CeltIC of Encounter Timing constraints: from  ... 
doi:10.1109/aspdac.2010.5419876 dblp:conf/aspdac/FanCL10 fatcat:xutnhzh32rbpril6b3ie6ro5p4

SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement

Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi
2008 2008 IEEE International Conference on Computer Design  
We target timing-critical paths postplacement and resynthesize and replace promising gates.  ...  Detail routing information allows incorporation of factors such as crosstalk, metal layer assignment and via delays which are crucial for accurate analysis.  ...  This is done for area minimization for meeting a timing constraint for a given technology library. The generated gate level netlist is then taken through the physical design flow.  ... 
doi:10.1109/iccd.2008.4751915 dblp:conf/iccd/KumarWD08 fatcat:mkcpr67b25gm3fof5lzlrkxqxe

An efficient technology mapping algorithm targeting routing congestion under delay constraints

Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
2005 Proceedings of the 2005 international symposium on physical design - ISPD '05  
Routing congestion has become a serious concern in today's VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints.  ...  These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delayoptimality of the solution using the notion of slack.  ...  This heuristic is similar to the one employed in [5] for the area minimization under delay constraints, where in spite of such a division of gate-areas at multiple fanout points, addition of the gate-areas  ... 
doi:10.1145/1055137.1055166 dblp:conf/ispd/ShelarSWS05 fatcat:trzshdaravaynmn4conddgtowm

Layout driven technology mapping

Massoud Pedram, Narasimha Bhat
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
Recent studies indicate that interconnections occupy more than hatf the total chip area and account for a significant part of the chip delay.  ...  In this paper, we present Lily, a technology mapper integrated with MIS, which considers layout area and wire delay during the technology dependent phase of logic synthesis.  ...  Lily maps a given logic circuit onto a set of gates in the target library such that t'oyout area and delay are minimized. The layout areais the sum of-gate areas and routing area.  ... 
doi:10.1145/127601.127635 dblp:conf/dac/PedramB91 fatcat:varb7gwlqfe67mvqwojrvpm3ie

Automatic Place&Route of Nano-magnetic Logic circuits

M. Vacca, S. Frache, M. Graziano, L. Di Crescenzo, F. Cairo, M. Zamboni
2013 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)  
We present results of an unprecedented Place & Route engine for Nano-magnetic logic, integrated in our tool for nanotechnologies design exploration.  ...  We developed and compared several algorithms to tackle Nano-magnetic Logic constraints and limitations, derived by real-life technological implementations, on complex combinational circuits (ISCAS85 benchmarks  ...  Fig. 8 . 8 A) Pins for channel definition. B) Mini Swap model for channel routing. C) Crosswire mapping. D) Physical mapping of interconnections.  ... 
doi:10.1109/nanoarch.2013.6623045 dblp:conf/nanoarch/VaccaFGCCZ13 fatcat:cxxzgndiznc7jpiql6oxwac7va

A predictive distributed congestion metric with application to technology mapping

R.S. Shelar, S.S. Sapatnekar, P. Saxena, Xinning Wang
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization.  ...  Experimental results on a set of benchmark circuits in a 90 nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows with marginal gate-area penalty  ...  The first author would like to thank Cristinel Ababei from the University of Minnesota and the members of PlatoCBD TM and Quasar TM teams at Intel Corporation for their invaluable help on the design flow  ... 
doi:10.1109/tcad.2005.846368 fatcat:cri44bfsjzgh7asr5l5w66he6i

A predictive distributed congestion metric and its application to technology mapping

Rupesh S. Shelar, Sachin S. Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2004 Proceedings of the 2004 international symposium on Physical design - ISPD '04  
This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization.  ...  Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions.  ...  Acknowledgment The first author would like to thank Cristinel Ababei from the University of Minnesota and the members of PlatoCBD TM and Quasar TM teams at Intel Corporation for their invaluable help on  ... 
doi:10.1145/981066.981111 dblp:conf/ispd/ShelarSSW04 fatcat:bunynkrfonendpun52374h5rvi

Combining Technology Mapping With Layout

Massoud Pedram, Narasimha Bhat, Ernest S. Kuh
1997 VLSI design (Print)  
Due to the significant contribution of interconnect to the area and speed of today's circuits and the technological trend toward smaller and faster gates which will make the effects of interconnect even  ...  In particular, this paper describes an integrated approach to technology mapping and physical design which finds solutions in both domains of design representation simultaneously and interactively.  ...  gate area logic delay cpu time gate area logic delay cpu time Table 1 goes here. 1 Table 2 : 2 Comparison of the total gate area and logic delay after placement and routing.  ... 
doi:10.1155/1997/73654 fatcat:6d3j563congtpeabr4is64izva

A Virtual CMOS Library Approach for Fast Layout Synthesis [chapter]

F. Moraes, M. Robert, D. Auvergne
2000 IFIP Advances in Information and Communication Technology  
The generator eliminates the need for postlayout compaction procedures and in addition produces parasitic capacitances estimations.  ...  The proposed method ean ehange the way layout synthesis is seen today, since aeeurate parasitie evaluation is an important prerequisite for optimized submieronie designs.  ...  The number of rows was chose to minimize the area, and fixed as a parameter for the generator.  ... 
doi:10.1007/978-0-387-35498-9_37 fatcat:tijf7xory5gtfcq4lxwcaa53ha

Placement-driven technology mapping for LUT-based FPGAs

Joey Y. Lin, Ashok Jagannathan, Jason Cong
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay.  ...  We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.  ...  For early technologies where gate delays were dominant, the objective of the technology mapping process was to minimize the depth of the mapped network.  ... 
doi:10.1145/611835.611836 fatcat:nnpjlgmlxza57f7ms3hn2rubfi

Placement-driven technology mapping for LUT-based FPGAs

Joey Y. Lin, Ashok Jagannathan, Jason Cong
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay.  ...  We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.  ...  For early technologies where gate delays were dominant, the objective of the technology mapping process was to minimize the depth of the mapped network.  ... 
doi:10.1145/611817.611836 fatcat:6qc7p4bs2bd2pd7gum5s6aq6yu
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