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Scratchpad sharing strategies for multiprocess embedded systems: a first approach

M. Verma, K. Petzold, L. Wehmeyer, H. Falk, P. Marwedel
2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.  
In this paper, we propose a set of optimal strategies to reduce the energy consumption of applications by sharing the scratchpad among multiple processes.  ...  Thus, power efficient processors coupled with onchip memories (e.g. caches, scratchpads) are the base of today's portable devices.  ...  In that respect, this is the first work on fully-analyzable scratchpad sharing techniques for multiprocess systems.  ... 
doi:10.1109/estmed.2005.1518087 dblp:conf/estimedia/VermaPWFM05 fatcat:k27qqx43jzhyhabvsqy5tiiyze

Improvement of multiprocessing performance by using optical centralized shared bus

Xuliang Han, Ray T. Chen, Randy A. Heyler, Ray T. Chen
2004 Photonics Packaging and Integration IV  
In this paper, the optical centralized shared bus is proposed for use in the multiprocessing systems.  ...  Meanwhile, from the architecture standpoint, it fits well in the centralized shared-memory multiprocessing scheme.  ...  ACKNOWLEDGEMENT The authors would like to thank BMDO, DARPA, ONR, AFOSR, and the ATP program of the State of Texas for supporting this work.  ... 
doi:10.1117/12.525754 fatcat:eafifuw5j5aidcnp53n6qn4gku

Scratchpad memory management in a multitasking environment

Bernhard Egger, Jaejin Lee, Heonshik Shin
2008 Proceedings of the 7th ACM international conference on Embedded software - EMSOFT '08  
We introduce a dynamic scratchpad memory code allocation technique for code that supports dynamically created processes.  ...  This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems running an operating system with preemptive multitasking.  ...  To increase performance and reduce the energy consumption, system designers make use of memory hierarchies to reduce off-chip memory accesses either by using hardware caches, scratchpad memories, or both  ... 
doi:10.1145/1450058.1450094 dblp:conf/emsoft/EggerLS08 fatcat:5uhfvmw4lnf3resmpky7ol5mzi

Trends in shared memory multiprocessing

P. Stenstrom, E. Hagersten, D.J. Lilja, M. Martonosi, M. Venugopal
1997 Computer  
The second step is to begin filling gaps in programming models and architectures for shared memory multiprocessing.  ...  P rogress in shared memory multiprocessing research has led to its industrial recognition as a key technology for application domains such as decision support systems and multimedia processing.  ...  Acknowledgments We thank Yale Patt, who initiated the set of task forces that allowed us to develop our thoughts in a creative environment in Hawaii.  ... 
doi:10.1109/2.642814 fatcat:mhsgglxwfvdrtc4c4ap6eshxxa

DEC OSF/1 Version 3.0 Symmetric Multiprocessing Implementation

Jeffrey M. Denham, Paula Long, James A. Woodward
1994 Digital technical journal of Digital Equipment Corporation  
The DEC OSF/1 version 3.0 operating system uses a number of techniques to achieve this goal.  ...  The primary goal for an operating system in a symmetric multiprocessing (SMP) implementation is to convert the additional computing power provided to the system, as processors are added, into improved  ...  ACKNOWLEDGMENTS Virtually every phase of this project depended on the teamwork and cooperation of multiple groups with the UNIX Software Group.  ... 
dblp:journals/dtj/DenhamLW94 fatcat:h24jjokff5c6da6qbut23fnmnu

A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation

Wei Qin, Joseph D'Errico, Xinping Zhu
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
Besides the advances of simulation techniques, ISS's have been mainly driven by the continuously improving performance of single processors.  ...  However, since the focus of processor manufacturers is shifting from frequency scaling to multiprocessing, ISS developers need to seize this opportunity for further performance growth.  ...  Subhendra Basu contributed to an early implementation of the presented approach. We thank the anonymous reviewers for their invaluable comments to improve the paper.  ... 
doi:10.1145/1176254.1176302 dblp:conf/codes/QinDZ06 fatcat:6h6nqh3xkzbrnhhayx2wj4ojoa

A High-Performance Parallel Algorithm to Search Depth-First Game Trees

Robert Morgan Hyatt
1988 ICGA Journal  
Three algorithms are developed to search depth-first game trees in parallel using a shared-memory mUltiprocessing computer system.  ...  This reduces synchronization overhead where a processor is out of work and has to wait on other processors to complete their work before moving to some other  ...  Three algorithms are developed to search depth-first game trees in parallel using a shared-memory mUltiprocessing computer system.  ... 
doi:10.3233/icg-1988-11411 fatcat:kb6fxfo7ujcsjhsibhtkwatq6u

INTER-PROCESSOR AND INTER-PROCESS COMMUNICATION IN REALTIME MULTI-PROCESS COMPUTING

M A Hossain, M O Tokhi
2002 IFAC Proceedings Volumes  
This paper presents an investigation into the inter-processor and inter-process communication for real-time computing in multiprocessing systems.  ...  Finally, a comparison of the results of the implementations is made on the basis of realtime performance to lead to merits of systems design incorporating fast processing techniques for real-time applications  ...  However, this is one of the slowest interprocessor communication techniques. A major drawback of this technique is how to handle reading and writing into the shared memory.  ... 
doi:10.3182/20020721-6-es-1901.00962 fatcat:52jt6ljbqbdv5e7fggq6skg7u4

MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee
2019 IEEE Access  
With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded systems is rapidly increasing.  ...  The prototype platform is synthesized with FPGA and Samsung 28 nm FD-SOI technology to verify the functional accuracy and small performance, area, and power overhead of the MMNoC.  ...  For example, an on-chip centralized hardware MMU module was presented for data allocation on the distributed shared memory space in the NoC-based MPSoC [22] .  ... 
doi:10.1109/access.2019.2923219 fatcat:hejulkauuvcljan4qiucdd2nzy

A Design of Pipelined Architecture for on-the-Fly Processing of Big Data Streams

Usamah Algemili, Simon Berkovich
2015 International Journal of Advanced Computer Science and Applications  
It reduces complexity, data dependency, high-latency, and cost overhead of parallel computing.  ...  The system overpasses internal memory constrains of multicore architectures by applying forced interrupts and crossbar switching.  ...  For instance, eight GPU boards that contains 6 MB of internal memory can allow up-to 48 MB of shared memory.  ... 
doi:10.14569/ijacsa.2015.060104 fatcat:rffyrbnqvvg5fczycrhze2i664

DMP

Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin
2009 Proceeding of the 14th international conference on Architectural support for programming languages and operating systems - ASPLOS '09  
In this paper we make the case for fully deterministic shared memory multiprocessing (DMP). The behavior of an arbitrary multithreaded program on a DMP system is only a function of its inputs.  ...  Current shared memory multicore and multiprocessor systems are nondeterministic.  ...  We also thank Karin Strauss, Dan Grossman, Susan Eggers, Martha Kim, Andrew Putnam, Tom Bergan and Owen Anderson from the University of Washington for their feedback on the manuscript.  ... 
doi:10.1145/1508244.1508255 dblp:conf/asplos/DeviettiLCO09 fatcat:hm2rmz7qe5cbbepymg22fro3xe

DMP

Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin
2009 SIGPLAN notices  
In this paper we make the case for fully deterministic shared memory multiprocessing (DMP). The behavior of an arbitrary multithreaded program on a DMP system is only a function of its inputs.  ...  Current shared memory multicore and multiprocessor systems are nondeterministic.  ...  We also thank Karin Strauss, Dan Grossman, Susan Eggers, Martha Kim, Andrew Putnam, Tom Bergan and Owen Anderson from the University of Washington for their feedback on the manuscript.  ... 
doi:10.1145/1508284.1508255 fatcat:nzvvj2kxerc3vlph4typ5qq5hy

DMP

Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin
2009 SIGARCH Computer Architecture News  
In this paper we make the case for fully deterministic shared memory multiprocessing (DMP). The behavior of an arbitrary multithreaded program on a DMP system is only a function of its inputs.  ...  Current shared memory multicore and multiprocessor systems are nondeterministic.  ...  We also thank Karin Strauss, Dan Grossman, Susan Eggers, Martha Kim, Andrew Putnam, Tom Bergan and Owen Anderson from the University of Washington for their feedback on the manuscript.  ... 
doi:10.1145/2528521.1508255 fatcat:i53avj67uvfg5dovopb6p7xjfi

Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters

Lei Chai, Albert Hartono, Dhabaleswar Panda
2006 2006 IEEE International Conference on Cluster Computing  
The design distinguishes small and large messages and handles them differently to minimize the data transfer overhead for small messages and the memory space consumed by large messages.  ...  While running the bandwidth benchmark, the measured L2 cache miss rate is reduced by half. The new design also improves the performance of MPI collective calls by up to 25%.  ...  Software Distribution: The design proposed in this paper will be available for downloading in upcoming MVAPICH releases.  ... 
doi:10.1109/clustr.2006.311850 dblp:conf/cluster/ChaiHP06 fatcat:odigrebu7fe55p34wmzurss73m

Process Migration Effects on Memory Performance of Multiprocessor Web-Servers [chapter]

Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
1999 Lecture Notes in Computer Science  
In order to limit false sharing overhead, we can adopt an accurate design of kernel data structures. Passive sharing can be reduced, or even eliminated, by using appropriate coherence protocols.  ...  We considered a shared-bus shared-memory multiprocessor as the simplest multiprocessor architecture to be used for accelerating Web-based and commercial applications.  ...  Cache affinity technique also reduces passive sharing transactions, so it does not improve PSCR performance.  ... 
doi:10.1007/978-3-540-46642-0_19 fatcat:5oo3m5l5rrahzkziww3vkr7fcq
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