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A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm

Nikolaos Alachiotis, Alexandros Stamatakis
2011 International Journal of Reconfigurable Computing  
We present the design of an efficient, pipelined floating-point datapath for calculating the logarithm function on reconfigurable devices.  ...  The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs.  ...  Acknowledgment Part of this work was funded under the auspices of the Emmy-Noether program by the German Science Foundation (DFG).  ... 
doi:10.1155/2011/341510 fatcat:qevfo7bvazhahjxwntmtawc4mu

Efficient floating-point logarithm unit for FPGAs

Nikolaos Alachiotis, Alexandros Stamatakis
2010 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)  
The logarithm is a widely used function in many scientific applications.  ...  We present the design of an efficient and sufficiently accurate Logarithm Approximation Unit (LAU) that uses a Look-Up Table ( LUT) based approximation, in reconfigurable logic.  ...  The algorithm exploits the way, by which floating point numbers are represented in the IEEE-754 standard.  ... 
doi:10.1109/ipdpsw.2010.5470752 dblp:conf/ipps/AlachiotisS10 fatcat:2ukof5vmabhcbhkgofjgifw36y

FPGA Optimizations for a Pipelined Floating-Point Exponential Unit [chapter]

Nikolaos Alachiotis, Alexandros Stamatakis
2011 Lecture Notes in Computer Science  
To this end, we present the design and implementation of a pipelined CORDIC/TD-based (COrdinate Rotation DIgital Computer/Table Driven) Exponential Approximation Unit (EAU) that will be made freely available  ...  In addition, a general framework for safely conducting application-specific optimizations of floating-point operators on FPGAs is presented.  ...  Furthermore, by SP, DP, and FP we denote IEEE-754 single precision arithmetics, IEEE-754 double precision arithmetics, and floating-point representations respectively.  ... 
doi:10.1007/978-3-642-19475-7_34 fatcat:uf45vg7gjfalnm7oxdh3rcs7nq

Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL

B. Akbarpour, A. T. Abdel-Hamid, S. Tahar, J. Harrison
2009 Computer journal  
In this paper, we have hierarchically formalized and verified a hardware implementation of the IEEE-754 table-driven floating-point exponential function algorithm using the HOL theorem prover.  ...  The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, starting from gate level implementation of the circuit  ...  by Harrison for the IEEE-754 table-driven floating-point exponential function.  ... 
doi:10.1093/comjnl/bxp023 fatcat:wvf6ehqqefaqtj6yhois52grmy

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip

Mantas Mikaitis, David R Lester, Delong Shang, Steve Furber, Gengting Liu, Jim Garside, Stefan Scholze, Sebastian Hoppner, Andreas Dixius
2018 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)  
Index Terms-exponential function, logarithm function, hardware accelerators, approximate arithmetic, fixed-point arithmetic, SpiNNaker2, neuromorphic computing, MPSoC 25 XXX-X-XXXXXXX-X-X/ARITH18/ c 2018  ...  To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon.  ...  Acknowledgements The authors would like to thank Felix Neumärker for suggestions about Verilog designs; Johannes Partzsch, Dongwei Hu, Michael Hopkins for the useful discussions and reviewers for their  ... 
doi:10.1109/arith.2018.8464785 dblp:conf/arith/MikaitisLSFLGSH18 fatcat:ph3mmzomsra2hpvy2dc6sa6jju

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

Pedro Echeverría, Marisa López-Vallejo
2011 Microprocessors and microsystems  
Keywords: Floating-point arithmetic FPGAs Library of operators High performance The high integration density of current nanometer technologies allows the implementation of complex floating-point applications  ...  A set of floating-point libraries composed of adder/ subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented.  ...  Acknowledgements This work has been partly funded by BBVA under Contract P060920579 and by the Spanish Ministry of Science and Innovation through the Project TEC2009-08589.  ... 
doi:10.1016/j.micpro.2011.04.004 fatcat:w5wzgj6uv5dbrc2hewnd3oueb4

Universal Numbers Library: design and implementation of a high-performance reproducible number systems library [article]

E. Theodore L. Omtzigt, Peter Gottschling, Mark Seligman, William Zorn
2020 arXiv   pre-print
We present the Universal Number Library, a high-performance number systems library that includes arbitrary integer, decimal, fixed-point, floating-point, and introduces two tapered floating-point types  ...  , posit and valid, that support reproducible arithmetic computation in arbitrary concurrency environments.  ...  by IEEE floating point.  ... 
arXiv:2012.11011v1 fatcat:jtkrzjbkqbbivkdtymthnmhk6a

Floating-Point Division Operator based on CORDIC Algorithm

Pongyupinpanich Surapong, Faizal Arya Samman
1970 ECTI Transactions on Computer and Information Technology  
A hardware architecture of CORDIC algorithm capable of processing broader input ranges is implemented and presented in this paper by using a pre-processing and a post-processing stage.  ...  In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation  ...  A brief survey of several floating-point division implementations in published articles is summarized in Table 5 .  ... 
doi:10.37936/ecti-cit.201371.54356 fatcat:du2eftzcfzaxznqtecaxbltajm

Efficient Floating-Point Implementation of the Probit Function on FPGAs

Mioara Joldes, Bogdan Pasca
2020 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
Floating-point arithmetic, minimax approximation, FPGA, quantile, inverse error function.  ...  Thus, the ICDF of the standard normal distribution, or probit function for short, is of particular interest.  ...  In this article we focus on the hardware floating-point (FP) implementation of the probit function, which is the inverse cumulative distribution function for the standard Gaussian distribution, also called  ... 
doi:10.1109/asap49362.2020.00036 dblp:conf/asap/JoldesP20 fatcat:gum7fcdyarf3tohatmdckqu5he

High-speed function approximation using a minimax quadratic interpolator

J.-A. Pineiro, S.F. Oberman, J.-M. Muller, J.D. Bruguera
2005 IEEE transactions on computers  
A table-based method for high-speed function approximation in single-precision floating-point format is presented in this paper.  ...  in the size of the look-up tables to be used, making our method very suitable for the implementation of an elementary function generator in state-ofthe-art DSPs or graphics processing units (GPUs).  ...  The method presented in this paper is a table-driven algorithm based on an enhanced minimax quadratic approximation which allows such high-speed computations in single-precision (SP) floating-point format  ... 
doi:10.1109/tc.2005.52 fatcat:kno2jv7nsnek3c2ivajlkxzuba

Sound Approximation of Programs with Elementary Functions [article]

Eva Darulova, Anastasia Volkova
2018 arXiv   pre-print
Unlike arithmetic, where the performance difference between for example single and double precision floating-point arithmetic is relatively small, elementary function calls provide a much richer tradeoff  ...  While their implementions in library functions are highly optimized, their computation is nonetheless very expensive compared to plain arithmetic. Full accuracy is, however, not always needed.  ...  Acknowledgments The authors thank Christoph Lauter for useful discussions and Youcef Merah for the work on an early prototype.  ... 
arXiv:1811.10274v1 fatcat:dtorpcayjrhxblyqbabyca4zrm

Code Generators for Mathematical Functions

Nicolas Brunie, Florent de Dinechin, Olga Kupriianova, Christoph Lauter
2015 2015 IEEE 22nd Symposium on Computer Arithmetic  
A typical floating-point environment includes support for a small set of about 30 mathematical functions such as exponential, logarithms and trigonometric functions.  ...  It may capture a much wider set of functions, and may capture even standard functions on nonstandard domains and accuracy/performance points.  ...  The 2008 revision of the IEEE 754 floating-point standard [3] has attempted a common standardization.  ... 
doi:10.1109/arith.2015.22 dblp:conf/arith/BrunieDKL15 fatcat:5dainnds2fblnkbara4lneoora

Rumpfr: A Fast and Memory Leak-free Rust Binding to the GNU MPFR Library

Tomoya Michinaka, Hideyuki Kawabata, Tetsuo Hironaka
2021 Journal of Information Processing  
The GNU MPFR library for arbitrary-precision floating-point arithmetic is widely used, and its Foreign Function Interface bindings to various languages have been developed.  ...  Rumpfr provides an interface that follows that of the MPFR library but hides the complexity of managing the mantissa area of floating-point numbers from the user.  ...  By using Rumpfr, programs for multiple-precision floating-point arithmetic with MPFR can be written efficiently in Rust.  ... 
doi:10.2197/ipsjjip.29.676 fatcat:xgcva4bisvbhhdsjte2y5sfomm

Composite Iterative Algorithm and Architecture for q-th Root Calculation

Alvaro V´zquez, Javier D. Bruguera
2011 2011 IEEE 20th Symposium on Computer Arithmetic  
The execution time and hardware requirements are estimated for single precision floating-point computations for several radices; this helps to determine which radices result in the most efficient implementations  ...  The algorithm is based on an optimized implementation of X 1/q = 2 (1/q) log 2 (X) by a sequence of parallel and/or overlapped operations: (1) reciprocal, (2) digit-recurrence logarithm, (3) left-to-right  ...  floating-point formats.  ... 
doi:10.1109/arith.2011.16 dblp:conf/arith/VzquezB10 fatcat:q263el6ohzbxddhtjfwmhnirji

A PDA-based Research Platform for Cochlear Implants

Arthur P. Lobo, Philip C. Loizou, Nasser Kehtarnavaz, Murat Torlak, Hoi Lee, Anu Sharma, Phillip Gilley, Venkat Peddigari, Lakshmish Ramanna
2007 2007 3rd International IEEE/EMBS Conference on Neural Engineering  
In this paper, we report on the real-time implementation of a 16-channel noiseband vocoder algorithm, which is a similar algorithm used in commercially available implant processors.  ...  Software development can be done either in C or in LabVIEW. The C implementation can be further optimized using Intel's primitive routines.  ...  Use of fixed-point arithmetic Since most PDAs lack floating-point arithmetic capabilities, we considered re-writing the code based on fixed-point arithmetic operations.  ... 
doi:10.1109/cne.2007.369603 fatcat:wjmcfpas5vc6lpbjjbuk42dmpu
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