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Asymmetrically banked value-aware register files for low-energy and high-performance
2008
Microprocessors and microsystems
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In this paper, we propose a new microarchitecture, the asymmetrically banked value-aware register file (AB-VARF), to exploit the prevailing narrow-width register values for low-latency and energy-efficient ...
Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. ...
Asymmetrically banked value-aware register files (AB-VARF)
Value-aware register files (VARF) Exploiting narrow-width values for energy reduction, a partitioned value-aware register file (P-VARF) was ...
doi:10.1016/j.micpro.2007.10.004
fatcat:rw6allqxtrduzfqvh4yblqgune
Asymmetrically Banked Value-Aware Register Files
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
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Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. ...
In this paper, we propose a new microarchitecture, the asymmetrically-banked value-aware register file (AB-VARF), to exploit the prevailing narrowwidth register values for low-latency and power-efficient ...
Asymmetrically-Banked Value-Aware Register Files (AB-VARF)
Value-Aware Register Files (VARF) Exploiting narrow-width values for power reduction, a partitioned value-aware register file (P-VARF) was proposed ...
doi:10.1109/isvlsi.2007.27
dblp:conf/isvlsi/WangYHZ07
fatcat:ci3tppztv5febp6onhwskq2odu
Empowering a helper cluster through data-width aware instruction selection policies
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. ...
We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load ...
In [14] and [20] , narrow width operands were exploited to reduce the power requirements of a value predictor. ...
doi:10.1109/ipdps.2006.1639350
dblp:conf/ipps/UnsalEVG06
fatcat:os6xaqbcyvgqhnxdqbkzwyjk24
Value Compression for Efficient Computation
[chapter]
2005
Lecture Notes in Computer Science
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A processor's energy consumption can be reduced by compressing values (data and addresses) that flow through a processor pipeline and gating off portions of data path elements that would otherwise be used ...
An approach for compressing all values running through a processor is proposed and evaluated. ...
[9] propose similar techniques for exploiting narrow width operands to reduce functional unit energy requirements and, at the same time, to increase performance. ...
doi:10.1007/11549468_59
fatcat:5ulgevlfqjhyje6j3j7e3uadcu
Dynamically exploiting narrow width operands to improve processor power and performance
1999
Proceedings Fifth International Symposium on High-Performance Computer Architecture
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In fact, another recent instruction set trend has been increased support for sub-word operations (that is, manipulating data in quantities less than the full word size). ...
The first, power-oriented, optimization reduces processor power consumption by using aggressive clock gating to turn off portions of integer arithmetic units that will be unnecessary for narrow bitwidth ...
Brooks is supported by an NSF Graduate Research Fellowship, and Martonosi by an NSF CAREER Award. ...
doi:10.1109/hpca.1999.744314
dblp:conf/hpca/BrooksM99
fatcat:fzuye3dof5a3bltdsqjuponase
Width-Partitioned Load Value Predictors
2003
Journal of Instruction-Level Parallelism
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For FCM predictors, width partitioning allows the total size of the second-level tables to be reduced by 75% while still maintaining the same prediction rates of a conventional FCM predictor. ...
Width-partitioning provides a 25.7-46.5% reduction in energy consumption for last value predictors and finite context matching (FCM) predictors. ...
Load Data-Width Properties Past studies have exploited the fact that the widths of data values in a program are not evenly distributed. ...
dblp:journals/jilp/Loh03
fatcat:phtsjegzdbfnblah6ukwizzv5a
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance
2000
ACM Transactions on Computer Systems
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The first, power-oriented optimization reduces processor power consumption by using operand-value-based clock gating to turn off portions of arithmetic units that will be unused by narrow-width operations ...
Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrow-width operations. ...
Negative numbers provide another source of narrow-width data for operand-based clock gating to exploit. ...
doi:10.1145/350853.350856
fatcat:ztn256zwcvahnchyjskwuhyxw4
On the Exploitation of Narrow-Width Values for Improving Register File Reliability
2009
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper, we propose to exploit narrow-width register values, which present the majority of the generated values, for making a duplicate of the value within the same data item; this in-register duplication ...
Index Terms-Reliability, soft errors, narrow-width value, register file, in-register duplication. ...
EXPLOITING NARROW-WIDTH REGISTER VALUES In this section, we present our reliable register file design that exploits the generated narrow-width register values. ...
doi:10.1109/tvlsi.2009.2017441
fatcat:ryrga5la2nfplaaafqpvrgf4te
Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches
2022
IEEE Access
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This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation ...
Experimental evaluation shows that the proposed technique improves performance by 14% on average compared to the baseline STT-MRAM cache. ...
By exploiting narrowwidth values, NPW avoids unnecessary write operations on some of the STT-MRAM cells if the data stored in the cache entry is narrow-width. ...
doi:10.1109/access.2022.3158493
fatcat:mggpgdocdbfvtkv4v42w2n6zsa
Exploiting narrow-width values for thermal-aware register file designs
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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In this paper, we perform a detailed study on the thermal behavior of a low-power value-aware register file (VARF) that is subjected to internal fine-grain hotspots. ...
The experimental results show that the ID-VARF can improve the performance by 26.1% and 7.2% over the conventional register file and the original VARF design, respectively. ...
From the perspective of power and power density optimization, we evaluate the original value-aware register file (VARF) design that exploits the majority narrow-width register values, i.e., data values ...
doi:10.1109/date.2009.5090887
dblp:conf/date/WangHZC09
fatcat:gscr7dinmvel5bjqiyngyhvhpa
An Adaptive Various-Width Data Cache for Low Power Design
2011
IEICE transactions on information and systems
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. 3) We exploit the redundancy of narrow-width values instead of compressed values, thus cache access latency does not increase. ...
In view of these observations, this paper proposes an Adaptive Various-width Data Cache (AVDC) to reduce the power consumption in a cache, which exploits the popularity of narrow-width value stored in ...
Acknowledgments We would like to thank the anonymous reviewers for invaluable and helpful comments on this paper. This research was ...
doi:10.1587/transinf.e94.d.1539
fatcat:lcldexpcm5acrmicuclmmk7eme
Reducing Soft Errors through Operand Width Aware Policies
2009
IEEE Transactions on Dependable and Secure Computing
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Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands ...
Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. ...
ISA extensions with operandwidth-specifying opcodes were proposed in [10] for energy efficiency. Power consumption of a value predictor was reduced by exploiting narrow operands in [40] . ...
doi:10.1109/tdsc.2008.18
fatcat:erebinw5pzditp57ad6vplnwjy
Bit section instruction set extension of ARM for embedded applications
2002
Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02
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These applications spend significant amounts of time packing and unpacking narrow width data into memory words. ...
4.26% to 27.27% and their code sizes are reduced by 1.27% to 21.05%. ...
Acknowledgements This work is supported by DARPA award F29601-00-1-0183 and National Science Foundation grants CCR-0220334, CCR-0208756, CCR-0105355, and EIA-0080123 to the University of Arizona. ...
doi:10.1145/581640.581642
fatcat:mazfyvoavjasfbwasuttkxf4vu
Bit section instruction set extension of ARM for embedded applications
2002
Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02
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These applications spend significant amounts of time packing and unpacking narrow width data into memory words. ...
4.26% to 27.27% and their code sizes are reduced by 1.27% to 21.05%. ...
Acknowledgements This work is supported by DARPA award F29601-00-1-0183 and National Science Foundation grants CCR-0220334, CCR-0208756, CCR-0105355, and EIA-0080123 to the University of Arizona. ...
doi:10.1145/581630.581642
dblp:conf/cases/LiG02
fatcat:fj2zvxpbhzcdnatqb6b2v74psy
Prioritizing verification via value-based correctness criticality
2007
2007 25th International Conference on Computer Design
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The proposed technique is accomplished by exploiting information redundancy of compressing computationally useful data bits. ...
A likelihood of correctness criticality is computed by a value vulnerability factor, which is defined by the numerically significant bit-width used to compute a result. ...
Parameter
Value
Fetch Queue Size
32 instructions
Fetch/Decode/Commit Width
4 instructions
Branch Predictor
4K entry BTB and hybrid predictor
Return Address Stack Size
16 entries
Physical Register ...
doi:10.1109/iccd.2007.4601921
dblp:conf/iccd/YooF07
fatcat:mbedrvsu6rb7hoeahvzucj6jb4
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