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CDF run IIb silicon vertex detector DAQ upgrade
2004
IEEE Transactions on Nuclear Science
VRB is a multiport memory designed to buffer and filter data for transfer to online processors. ...
The electrical protocol of the front and back panels of FTM are LVDS (JPC interface) and TTL (FIB interface), respectively. ...
doi:10.1109/tns.2004.839065
fatcat:dcx72ourfvgkhb74wsumydkpwq
CDF run IIb silicon vertex detector DAQ upgrade
2003
2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515)
VRB is a multiport memory designed to buffer and filter data for transfer to online processors. ...
The electrical protocol of the front and back panels of FTM are LVDS (JPC interface) and TTL (FIB interface), respectively. ...
doi:10.1109/nssmic.2003.1351893
fatcat:rgo6toemwngavibdahjxgjcfji
The Maxc Systems
1978
Computer
However, two time-consuming checkout problems were disk transfers (including interrupt system) and multiport memory competition. ...
two special bus destinations that route instructions and indirect words into registers; and (3) a bus destination and bus source to manipulate byte pointers. ...
doi:10.1109/c-m.1978.218184
fatcat:q5bn52bkmvgfnfpyj3fa6wfnzy
The Prospects for Multivalued Logic: A Technology and Applications View
1981
IEEE transactions on computers
single line bus. ...
The IC's shown are TTL open-collector switches. The original design shown in (
. 20. ...
doi:10.1109/tc.1981.1675860
fatcat:flg5qwebifb6vf6fguy7s2igyy
CMOS active pixel image sensors for highly integrated imaging systems
1997
IEEE Journal of Solid-State Circuits
The arrays feature random access, 5-V operation and transistortransistor logic (TTL) compatible control signals. ...
A family of CMOS-based active pixel image sensors (APS's) that are inherently compatible with the integration of onchip signal processing circuitry is reported. ...
High frame rate imaging is also possible with modified transistor sizing and multiport readout. ...
doi:10.1109/4.551910
fatcat:ohhfuyd5sjeatfonm3vv64isse
Forwarding metamorphosis
2013
Computer communication review
decrements the TTL. ...
Statistics consume 24 memory banks, along with a spare bank for multiporting the statistics memory. ...
doi:10.1145/2534169.2486011
fatcat:lvfly3ovmfgpjgi7qba2cmswrm
Forwarding metamorphosis
2013
Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM - SIGCOMM '13
decrements the TTL. ...
Statistics consume 24 memory banks, along with a spare bank for multiporting the statistics memory. ...
doi:10.1145/2486001.2486011
dblp:conf/sigcomm/BosshartGKVMIMH13
fatcat:pfurwqmtxjbmroqtvjs6xpasx4
The click modular router
2000
ACM Transactions on Computer Systems
On conventional PC hardware, the Click IP router achieves a maximum loss-free forwarding rate of 333,000 64-byte packets per second, demonstrating that Click's modular and flexible architecture is compatible ...
For example, DecIPTTL decides if a packet's time-tolive field (TTL) has expired. ...
It is limited by the PCI bus, not the CPU, which explains its different behavior under overload. ...
doi:10.1145/354871.354874
fatcat:dl3s5dda55fpfdxhejciwqxmke
The Virtual Bus: A Network Architecture Designed to Support Modular-Redundant Distributed Periodic Real-Time Control Systems
[article]
2022
Multiple virtual buses can coexist simultaneously in a single network, as the resources allocated to each bus are orthogonal in either space or time. ...
The Virtual Bus architecture is not a purely theoretical concept; a small research platform has been constructed for development, testing and demonstration purposes. ...
It is possible that an AN may be unable to offer compatible resources to a virtual bus that is being constructed. ...
doi:10.25911/0sff-zr24
fatcat:lwejvbqwtbgalleyf7pmqs6nga
Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces
[article]
2019
Moreover, with a bus of 64-bit, two pixels can be transferred at the same time. ...
]
Time
Synchronization
[TTL]
HDMI
Controller
TTL
Generator
TTL
Generator
Images
608x684 pixels
[HDMI]
I/O Data
Interface
Camera Link
Deserializer
Data from
BioCam X
[Camera Link ...
doi:10.15167/seu-giovanni-pietro_phd2019-05-02
fatcat:smibmdaxojedbi5jzumgxjvxee
Background and Introduction
[chapter]
Implementing Voice over IP
Packet Voice Bu¤ering for Delay Jitter Compensation In packet-switched networks, bu¤ering serves many useful and repugnant purposes. ...
ITU-T recommends the specifications in G.764 and G.765 standards [5, 6] for carrying packetized voice over ISDN-compatible networks. ...
TTL Time to live; a field in an IP header that indicates how long a packet is allowed to traverse a network as a valid entity before being dropped. ...
doi:10.1002/0471225274.ch1
fatcat:mkgx3pgzhnfo3kp3h46ne4twk4
LUX-ZEPLIN (LZ) Conceptual Design Report
[article]
2015
arXiv
pre-print
Readout of the FPGA data can be performed either via the memory bus or via the FIFOs, depending on the application. ...
A dual-core processor will be connected to the FPGA with the 32-bit memory bus, as well as two dedicated 16-bit-wide FIFOs. ...
arXiv:1509.02910v2
fatcat:ru5rfon2ejc2zokc6jldpcoege
A study of the entrainment and turbulence in a plane buoyant jet
[article]
1975
II ttl mJ...Zr I ...!2t:::::. IJ....
~__ ____ ~ ____ ~ ____ ~ ____ ~r-_ ___ ~ __ -OS·L OO·S OS·n OO-E OS-! ...
Rapid dilution can be accomplished with a multiport diffuser structure in which jets from numerous ports spaced along the ocean outfall merge and form a twodimensional buoyant jet. ...
doi:10.7907/z9k935g2
fatcat:ttvqovxz7nal3ohxqlyzr6t27i
Multifuel Burners
[chapter]
2014
Combustion Engineering and Gas Utilisation
In a multiport burner it is the sum of the areas of all the ports. ...
In a multiport burner it is the sum of the areas of all the ports. ...
doi:10.4324/9781315024714-10
fatcat:w4epumpwrzeqji2u6jpj4xfyqy