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TMA: Tera-MACs/W Neural Hardware Inference Accelerator with a Multiplier-less Massive Parallel Processor [article]

Hyunbin Park, Dohyun Kim, Shiho Kim
2019 arXiv   pre-print
We propose a Tera-MACS/W neural hardware inference Accelerator (TMA) with 8-bit activations and scalable integer weights less than 1-byte.  ...  The proposed neural processing element has Multiplier-less Massive Parallel Processor to work without any multiplications, which makes it attractive for energy efficient high-performance neural network  ...  We propose a Tera-MACS/W neural hardware inference accelerator (TMA) with a multiplier-less massive parallel processor with 8-bit integer activations and integer weights less than 1-byte.  ... 
arXiv:1909.04551v1 fatcat:hkm7dcmagzf7de3nqzs5ifq4e4