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Scale-out Systolic Arrays [article]

Ahmet Caner Yüzügüler, Canberk Sönmez, Mario Drumond, Yunho Oh, Babak Falsafi, Pascal Frossard
2022 arXiv   pre-print
In this work, we study three key pillars in multi-pod systolic array designs, namely array granularity, interconnect, and tiling.  ...  We propose Scale-out Systolic Arrays, a multi-pod inference accelerator for both single- and multi-tenancy based on these three pillars.  ...  WHY SCALE-OUT SYSTOLIC ARRAYS?  ... 
arXiv:2203.11540v1 fatcat:pqbxwye6zvai7fzsbpw2xzad44

General-purpose systolic arrays

K.T. Johnson, A.R. Hurson, B. Shirazi
1993 Computer  
Behrooz Shirazi, University of Texas, Arlington Systolic arrays effectively exploit massive parallelism in computationally intensive applications.  ...  have imagined how quickly workstations would revolutionize computing.  ...  Why systolic arrays? Ever since Kung proposed the systolic model..' its elegant solutions to demanding problems and its potential performance have attracted great attention.  ... 
doi:10.1109/2.241423 fatcat:5pbdb7wypbbqzk7riagtv5jsvq

Wafer-scale integration of systolic arrays

Frank Thomson Leighton, Charles E. Leiserson
1982 23rd Annual Symposium on Foundations of Computer Science (sfcs 1982)  
We also discuss applications of the work to problems in VLSI layout theory, graph theory, fault-tolerant systems, planar geometry, and the probabilistic analysis of algorithms.  ...  than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and  ...  Raffel for acquainting them with the details of their work and for providing the photographs in Figs. 2, 3 , and 4. Special thanks in particular to J. Siskind and J.  ... 
doi:10.1109/sfcs.1982.49 dblp:conf/focs/LeightonL82 fatcat:6dchkmhl2bcyliyr266ziwpluy

Wafer-Scale Integration of Systolic Arrays

Leighton, Leiserson
1985 IEEE transactions on computers  
-Key Words'channel width, fault-tolerant systems, probabilistic analysis, spannin tree, Bystolic arrays, travelling salesman problem, tree of meshes, VLSI, wafer-scale integration, wire Thi neearch was  ...  We also discuss applications of this work to problems in VLSI layout theory, graph theory, fault-tolerant systems and planar geometry.  ...  2, 3 , and 4.  ... 
doi:10.1109/tc.1985.1676584 fatcat:d7nrl5ubqbgkhepwnkejicdaxu

Systolic (VLSI) arrays for relational database operations

H. T. Kung, Philip L. Lehman
1980 Proceedings of the 1980 ACM SIGMOD international conference on Management of data - SIGMOD '80  
These (systolic) processor arrays arc readily and COstrcffcctivcly implementable with prcscnl teclirrolo~,y, due to lhc .cxlrer& simplicity of their process&s, and the I1izl-i regularity of th&r intcrconncction  ...  ly on networks of prdccssors havine an array strurturc.  ...  Dztabasc Co'nsidarations 2.1 Systolic Arrays Regular geometric structures arc typically used in systolic arrays.  ... 
doi:10.1145/582250.582267 dblp:conf/sigmod/KungL80 fatcat:zf2w7nazgbaztbgiwjg22hmlwu

FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays [article]

Surya Selvam, Vinod Ganesan, Pratyush Kumar
2021 arXiv   pre-print
The resultant computation is systolic and efficiently utilizes the systolic array with a slightly modified dataflow.  ...  For example, MobileNet uses depthwise separable convolution to achieve much lower latency, while systolic arrays provide much higher performance per watt.  ...  We thank Gokulan for his help in modeling systolic-arrays. Finally, we thank the anonymous reviewers for their insightful comments and suggestions towards improving the work.  ... 
arXiv:2105.13434v1 fatcat:gjnzf7mnabeoti2cc5zol47iaq

Systolic Arrays for Lattice-Reduction-Aided MIMO Detection [article]

Ni-Chun Wang, Ezio Biglieri, Kung Yao
2011 arXiv   pre-print
In this paper we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD.  ...  Comparisons between the two algorithms in terms of bit-error-rate performance, and average FPGA processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture  ...  The system model and how LRAD works are briefly described in Section II.  ... 
arXiv:1101.3698v1 fatcat:vsdc57msovc7fbtgjzrc62xonm

Unified VLSI systolic array design for LZ data compression

Shih-Arn Hwang, Cheng-Wen Wu
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression.  ...  A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable.  ...  The main difference between systolic arrays and other architectures is that systolic arrays can achieve a higher clock rate (due to nearest-neighbor communication) and can easily be implemented and tested  ... 
doi:10.1109/92.931226 fatcat:mnnlipxa3bclncbjoqqh37tmia

Non-invasive investigations of the right heart: How and why?

Christine Selton-Suty, Yves Juillière
2009 Archives of Cardiovascular Diseases  
right atrial pressure RV right ventricular RVEF right ventricular ejection fraction RV FAC right ventricular fractional area change RVOT right ventricular outflow tract TAPSE tricuspid annular plane systolic  ...  However, due to both its shape and location and to the load dependence of its ejection fraction, accurate evaluation of its function is still a challenge.  ...  At present, imaging is performed on 1.5 to 3 Tesla systems, using dedicated cardiac phased-array coils with multiple elements and electrocardiogram triggering.  ... 
doi:10.1016/j.acvd.2008.12.010 pmid:19375676 fatcat:ftxmdodupzgo5ocqin7xoes7fe

Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks

Rui Xu, Sheng Ma, Yaohua Wang, Xinhai Chen, Yang Guo
2021 ACM Transactions on Architecture and Code Optimization (TACO)  
At the same time, CMSA and the traditional systolic arrays are similar in area and energy consumption.  ...  The biggest advantage of the systolic array architecture is its simple and efficient design principle.  ...  This is why many hardware accelerators choose the systolic array architecture.  ... 
doi:10.1145/3460776 fatcat:lnae5l5oo5bozout4hnuasrbaa

Assessment of left ventricular diastolic function by MR: why, how and when

Ricardo Duarte, Gabriel Fernandez
2010 Insights into Imaging  
Cardiovascular magnetic resonance (CMR), a valuable non-invasive technique for the evaluation of the cardiovascular system, has already been accepted as the "gold standard" for the assessment of systolic  ...  ECG-triggering phase-contrast (PC) CMR allows the routine assessment of diastolic function by measuring the transmitral and pulmonary venous flow with high accuracy and reproducibility, using morphological  ...  phased array cardiac dedicated coil.  ... 
doi:10.1007/s13244-010-0026-7 pmid:22347914 pmcid:PMC3259379 fatcat:urjiz5iqwne7djk56hovr7hmzy

Decimator Systolic Arrays Design Space Exploration for Multirate Signal Processing Applications

Mohammed Shoukry, Fayez Gebali, Pan Agathoklis
2019 IET Circuits, Devices & Systems  
Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated.  ...  This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler.  ...  Table 1 illustrates how nine possible systolic array design options are obtained.  ... 
doi:10.1049/iet-cds.2019.0077 fatcat:cnmv7z5d2jdp7irragx7jpqzdu

Designing of processor-time optimal systolic arrays for band matrix-vector multiplication

I.ſ. Milovanović, E.I. Milovanović, I.Z. Milentijević, M.K. Stojčev
1996 Computers and Mathematics with Applications  
Figure 3 . 3 Data Figure 4 . 4 Data flow in the array S3 (direction ,u( l,O, 1)). and Fortes [lo] and Miranker and Winkler [ll] worked on how to minimize the computation time of a systolic array.  ...  There have been several works on how to synthesize optimal systolic array architectures, with each work concentrating on certain optimization criterion.  ...  The number of PEs in systolic array S3 is R = n and active execution time is T,,, = 2n -1 time units.  ... 
doi:10.1016/0898-1221(96)00100-9 fatcat:ghknbcrnxrgrdni3ddd7kiyytm

High Level Synthesis Implementation of a Three-dimensional Systolic Array Architecture for Matrix Multiplications on Intel Stratix 10 FPGAs [article]

Paolo Gorlani, Christian Plessl
2021 arXiv   pre-print
In this paper, we consider the HLS implementation of a three-dimensional systolic array architecture for matrix multiplication that targets specific characteristics of Intel Stratix 10 FPGAs in order to  ...  The investigated three-dimensional systolic array architecture is able to produce hardware designs that use 99% of the available DSPs with maximum frequencies that let us achieve performances above 3 TFLOPS  ...  How to connect the systolic array architecture to the global memory system since a global memory LSU is not able to provide enough data throughput in order not to stall the pipeline?  ... 
arXiv:2110.11521v1 fatcat:tvyelfepqrdbldu4adpv7a33tu

Why systolic architectures?

Kung
1982 Computer  
0 This article reviews the basic principle of systolic architectures and explains why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.  ...  The systolic architectural concept was developed at Carnegie-Mellon University,'17 and versions of systolic processors are being designed and built by several industrial and governmental organizations.84  ...  Therefore, questions such as how a computation can be decomposed to minimize I/O, how the I/O requirement is related to the size of a specialpurpose system and its memory, and how the I/O bandwidth limits  ... 
doi:10.1109/mc.1982.1653825 fatcat:7ciz7pfl7fdcra4ljse4p3raju
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