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Systolic Architecture of Adaptive Post Detection Integration CFAR Processor in Binomial Distribution Pulse Jamming [chapter]

Ivan Garvanov, Christo Kabakchiev, Plamen Daskalov
<span title="">2004</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
A new parallel algorithm for signal processing and a parallel systolic architecture of a CFAR processor with adaptive censoring and post detection integration (API) are presented in the paper.  ...  The processor proposed is used for target detection when echoes from targets are performed in conditions of binomial distribution pulse jamming.  ...  Parallel Architecture of an API CFAR Processor The systolic parallel architecture of a CA CFAR processor with adaptive censoring and non-coherent integration is presented on Fig.5 , and it is similar  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="">doi:10.1007/978-3-540-24588-9_51</a> <a target="_blank" rel="external noopener" href="">fatcat:spmachcl3ja7ta7qpldbl6i7t4</a> </span>
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