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A VHDL-AMS Case Study [chapter]

C. Lallement, F. Pêcheux, Y. Hervé
2002 IFIP Advances in Information and Communication Technology  
We present the principles, techniques and tools used to achieve the incremental implementation of an analytical third generation Spice transistor MOST model named EKV in VHDL-AMS, with relevant parameters  ...  The model includes the capacitances and resistors induced by the LDD structures as a function of gate voltage, and also considers thermo-electrical interactions between the transistor and its direct environment  ...  ACKNOWLEDGMENTS The authors thank Matthias Bucher for discussion on the implementation of layout-dependent resistors model (without bias dependent) in standard simulators, and Fabien Pregaldiny for his  ... 
doi:10.1007/978-0-387-35597-9_30 fatcat:edeqft7syze7xlnegbetdym4ki

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages

Ashish Alape Vivekananda, Eduard Enoiu
2020 Designs  
We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL.  ...  search for test cases in these academic studies.  ...  Acknowledgments: We would like to thank the anonymous reviewers for their useful suggestions and comments. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/designs4030031 fatcat:izwpetzp55ebxe5trhxhes4hii

VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow

F. Ferrandi, G. Ferrara, R. Palazzo, V. Rana, M.D. Santambrogio
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
To validate the entire methodology, we have performed a comparison based on the CoreConnect communication infrastructure, between our results with the classical Xilinx design flow using EDK and ISE.  ...  The proposed approach implements all the communication infrastructure needed by a component, described in VHDL, to be finally inserted into a real architecture that can be implemented on FPGAs, reducing  ...  A REAL CASE STUDY: CARONTE In this section we will discuss how to apply the proposed methodology into a real working flow, Caronte, for the implementation of a dynamic reconfigurable system using a common  ... 
doi:10.1109/ipdps.2006.1639491 dblp:conf/ipps/FerrandiFPRS06 fatcat:zfnrghhlc5b7dk63yfthdt6jym

Formal verification of VHDL using VHDL-like ACL2 models [chapter]

Dominique Borrione, Philippe Georgelin
2001 Electronic Chips & Systems Design Languages  
When a design reaches the register transfer level, essential architectural decisions have been taken; their validation required extensive simulation of the abstract behavioral specifications.  ...  We propose to introduce mechanically supported formal reasoning in the design flow, by producing a model of VHDL behavioral specifications in the logic of the ACL2 theorem prover.  ...  Acknowledgements: The authors are thankful to Vanderlei Moraes Rodrigues for fruitful discussions and helpful comments on a previous version of this paper. References  ... 
doi:10.1007/978-1-4757-3326-6_23 fatcat:ndvyegcjmbftnpozdurmxljsmi

VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL [chapter]

Ernst Christen, Kenneth Bakalar
1997 Current Issues in Electronic Modeling  
They require the VHDL 1076.1 language to be a superset of VHDL 1076VHDL -1993 [2] [2], supporting the hierarchical description and the simulation of continuous and mixed continuous/discrete systems with  ...  The VHDL 1076.1 language satisfies a set of requirements that have been documented in the 1076.1 Design Objective Document (IEEE PAR 1076.1 1995).  ...  Introduction IEEE VHDL 1076-1993 (The VHSIC Hardware Description Language) is designed for the description and simulation of digital systems, supporting modeling at various levels of abstractions.  ... 
doi:10.1007/978-1-4615-6297-9_2 fatcat:pz5qpvjm6fd2nkwzru4hnaqmg4

Using VHDL for board level simulation

S. Habinc, P. Sinander
1996 IEEE Design & Test of Computers  
(For more about ESA and its choice of VHDL, see the box.) A logical follow-on activity to using VHDL modeling for ASIC design verification is to model and simulate complete board designs.  ...  Board level simulation supports a top-down methodology allowing simulation of unimplemented boards, which enables designers to work with incomplete specifications of a system or component and to verify  ...  We also thank all those discussing simulation performance in their papers and on the Internet from whom we have gathered input for our work.  ... 
doi:10.1109/54.536097 fatcat:fcxdbpo4rjejxlz5yzaoavylca

Python as a hardware description language: A case study

J.I. Villar, J. Juan, M.J. Bellido, J. Viejo, D. Guerrero, J. Decaluwe
2011 2011 VII Southern Conference on Programmable Logic (SPL)  
This study is based on the independent application of Verilog and Python based flows to the development of a real peripheral.  ...  In this contribution, the approach proposed by the MyHDL package to use Python as an HDL is analyzed by making a comparative study.  ...  INTRODUCTION The design of digital electronic systems, since its inception, was marked by a parallel and steady increase of both the complexity of tackled designs and the performance and integration level  ... 
doi:10.1109/spl.2011.5782635 fatcat:fsxlwurkjbdidoyio6audtjktm

Model Based Testing of VHDL Programs

Tolga Ayav, Tugkan Tuglular, Fevzi Belli
2015 2015 IEEE 39th Annual Computer Software and Applications Conference  
Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor.  ...  VHDL programs are often validated by means of test benches constructed from formal system specification.  ...  A subset of VHDL, called synthesizable VHDL, is used for register transfer level (RTL) design, i.e., the first stage of digital integrated circuit design.  ... 
doi:10.1109/compsac.2015.198 dblp:conf/compsac/AyavTB15 fatcat:ljxozpad35hgdanarqsouae7su

Software methodologies in VHDL code analysis

Cristiana Bolchini, Luciano Baresi
1997 Journal of systems architecture  
At a high level of abstraction, the VHDL specification of the functionalities that a circuit shall perform is given by defining the behavioral model.  ...  A necessary condition to discover deadlocks is, thus, the presence of loops within the graph. Dependencies graphs apply to both closed systems and open systems.  ...  It sounds very similar to faults models introduced in VHDL analysis: it could be tried to define the mutations of a VHDL specification and to study the relations with fault models.  ... 
doi:10.1016/s1383-7621(97)00024-6 fatcat:7534go5rsfgkpm3f7pv2y7vni4

vMAGIC—Automatic Code Generation for VHDL

Christopher Pohl, Carlos Paiz, Mario Porrmann
2009 International Journal of Reconfigurable Computing  
In this paper, VHDL Manipulation and Generation Interface (vMAGIC), a Java library to read, manipulate, and write VHDL code is presented.  ...  The basic functionality as well as the designflow is described, stressing the advantages when designing with vMAGIC.  ...  on its behalf and funded by the Deutsche Forschungsgemeinschaft.  ... 
doi:10.1155/2009/205149 fatcat:nwny3lgchzez5o5r53vca3ledm

VHDL observers for clock constraint checking

Charles Andre, Frederic Mallet, Julien DeAntoni
2010 International Symposium on Industrial Embedded System (SIES)  
Logical time has proved very useful to model heterogeneous and concurrent systems at various abstraction levels.  ...  The Clock Constraint Specification Language (CCSL) uses logical clocks as first-class citizens and supports a set of (logical) time patterns to specify the time behavior of systems.  ...  In this paper, we have detailed how to use a CCSL specification for the automatic generation of VHDL observers, linking together high level specifications and low level analyses.  ... 
doi:10.1109/sies.2010.5551372 dblp:conf/sies/AndreMD10 fatcat:d6ujwplqmfa3fb2syidnh6ja4a

Design-Flow and Synthesis for ASICs: A Case Study

Massimo Bombana
1995 Proceedings - Design Automation Conference  
The problem of relating the different abstraction levels involved in the extended design process is solved through the use of logic synthesis tools.  ...  The resulting design methodology combining both formal and more traditional design tools has been tested on a complex device in the area of telecommunications.  ...  There are problems in knowing if the appropriate test-sets really do cover the anticipated behavior and use of the system being designed.  ... 
doi:10.1109/dac.1995.249962 fatcat:5ulddl4rrraqpgz5wleeb5o6du

System performance modeling with functional schemes and VHDL

P. Bakowski, J.-P. Calvez
1992 Microprocessing and Microprogramming  
Multiple-process behavioral synthesis for mixed hardware-software systems,  ...  Calvez, A CoDesign Case Study with the MCSE Methodology, in the journal "Design Automation of Embedded Systems", Special issue on "Embedded Systems Case Studies", vol.1 n 0 3, , 1996, pp 183-211.  ...  Calvez, A System Specification Model and Method, in Current Issues In Electronic Modeling, Volume 4: High-Level System Modeling: Specification and Design Methodologies, R. Waxman, J.M. Bergé, O.  ... 
doi:10.1016/0165-6074(92)90328-5 fatcat:355us6s5jnfwlgtnvnaauugjca

Automotive VHDL-AMS Electro-Mechanics Simulations [chapter]

Mariagrazia Graziano, Massimo Ruo
2011 New Trends and Developments in Automotive System Engineering  
Metzner & Schafer, 2002) a methodology for VHDL-AMS based specification, design and verification of an automotive Smart Power IC is presented.  ...  On the author knowledge, often in the industrial field specific design values are not defined on a rigorous basis, but, on the contrary, chosen using a trial and error methodology.  ... 
doi:10.5772/13154 fatcat:tdl24h4t45hv3gxeovrpnku6hm

A case study of hardware and software synthesis in ForSyDe

Zhonghai Lu, Ingo Sander, Axel Jantsch
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
In this paper we illustrate with a case study of a digital equalizer how a ForSyDe model can be synthesized into a hardware, a software or a combined hardware/software implementation.  ...  ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts.  ...  Though HML uses some features of Standard ML, such as polymorphic functions and its type system, it is mainly an improvement of VHDL, while our system specification is on a significantly higher abstraction  ... 
doi:10.1145/581214.581219 fatcat:g2kw44clh5egpo7xek2h4czh4q
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