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Grammar-based design of embedded systems

Johnny Öberg, Mattias O'Nils, Axel Jantsch, Adam Postula, Ahmed Hemani
2001 Journal of systems architecture  
, and to the virtual prototyping of DSP systems.  ...  Only in recent years grammar-based design has become a promising research ®eld and the ®rst commercial tools have appeared on the market.  ...  and virtual prototyping of complex DSP systems [8] .  ... 
doi:10.1016/s1383-7621(00)00047-3 fatcat:mbxpsziqu5evfjeznqkqvh6zly

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia (+2 others)
2013 Microprocessors and microsystems  
Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping.  ...  As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping.  ...  From these annotated components a virtual prototype is generated. This prototype is used to estimate the power and timing of the overall system.  ... 
doi:10.1016/j.micpro.2013.09.001 fatcat:7a5ycc45m5h7nkjhxhe4u2j7am

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, Zhiru Zhang
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA  ...  Escalating System-on-Chip design complexity is pushing the design community to raise the level of abstraction beyond RTL.  ...  Verification drives the acceptance of high-level specification: Transaction-level modeling (TLM) with SystemC [107] or similar C/C++ based extensions has become a very popular approach to system-level  ... 
doi:10.1109/tcad.2011.2110592 fatcat:rr75vomr6zf5vhgs3swjblslza

A compiler infrastructure for embedded heterogeneous MPSoCs

Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid
2013 Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM '13  
Programming heterogeneous MPSoCs (Multi-Processor Systems on Chip) is a grand challenge for embedded SoC providers and users today.  ...  In this paper, we argue for the need and significance of positioning the language and tool design from the perspective of practicality to address this challenge.  ...  Virtual prototypes of MPSoC platforms (e.g. Synopsys MCO [25] ) are also supported, and other multicore platforms (mostly x86 or ARM based) where a Pthreads environment is available.  ... 
doi:10.1145/2442992.2442993 dblp:conf/ppopp/ShengSOBVLA13 fatcat:acfnugkt5jalvb45jadvmr35xm

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  Nevertheless, every application field introduces special requirements to the used computational architecture.  ...  of future ASICs.  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

Formal ESL Synthesis for Control-Intensive Applications

Michael F. Dossis
2012 Advances in Software Engineering  
Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to  ...  The scheduler PARCS and the formal compilation of the system are tested with a number of benchmarks and real-world applications.  ...  Therefore, using the general I/O handshake of this approach, extremely complex systems can be delivered in a fraction of time which is needed when using platform or IP based approaches.  ... 
doi:10.1155/2012/156907 fatcat:f55w3dv6crflzfqinksfrcahnu

Pushing the Level of Abstraction of Digital System Design: a Survey on How to Program FPGAs

Emanuele Del Sozzo, Davide Conficconi, Alberto Zeni, Mirko Salaris, Donatella Sciuto, Marco D. Santambrogio
2022 ACM Computing Surveys  
They are state-of-the-art for prototyping, telecommunications, embedded, and an emerging alternative for cloud-scale acceleration.  ...  We review these abstraction solutions, provide a timeline, and propose a taxonomy for each abstraction trend: programming models for HDLs; IP-based or System-based toolchains for HLS; application, architecture  ...  Our analysis highlights how such approaches provide a higher abstraction level than (System)Verilog and VHDL when designing FPGA-based systems.  ... 
doi:10.1145/3532989 fatcat:nsk5lwvt3vba5fbxmaj7sgpwru

SMT-8036 Based Implementation of Secured Software Defined Radio System for Adaptive Modulation Technique [chapter]

Sudhanshu Mehta, Surbhi Sharma, Rajesh Khanna
2011 Communications in Computer and Information Science  
It can be used for prototyping 3G (3 rd generation) systems and high-speed data acquisition system with or without digital processor.  ...  Developments of RTES include modeling activities, using languages based on either grammars or metamodels, as well as analysis activities such as formal validation or simulation.  ... 
doi:10.1007/978-3-642-22720-2_20 fatcat:efjaizgqdvdbhppaju5fqtltfi

Compiling Scilab to high performance embedded multicore systems

Timo Stripf, Oliver Oey, Thomas Bruckschloegl, Juergen Becker, Gerard Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias (+5 others)
2013 Microprocessors and microsystems  
a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction.  ...  The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of  ...  The estimation will be based on static analysis of the NAC code executed on the NAC virtual machine using compiled simulation.  ... 
doi:10.1016/j.micpro.2013.07.004 fatcat:pdh6kpwp25galdrdtvpv45l2cy

Secure and Dependable Multi-Cloud Network Virtualization

Max Alaluna, Eric Vial, Nuno Neves, Fernando M. V. Ramos
2017 Proceedings of the 1st International Workshop on Security and Dependability of Multi-Domain Infrastructures - XDOMO'17  
We implemented a prototype of Sirius, and evaluated all solutions using both large scale simulations and a real testbed environment running our prototype.  ...  Our evaluations demonstrate that the system scales well for networks of thousands of switches employing diverse topologies and improves on the virtual network acceptance ratio and provider profit when  ...  is very close to the renew approach, and it improves 17% with DSP-K2.  ... 
doi:10.1145/3071064.3071066 fatcat:timnf66ocbafnb4f6xh5xlfofi

Policy-Driven Memory Protection for Reconfigurable Hardware [chapter]

Ted Huffmire, Shreyas Prasad, Tim Sherwood, Ryan Kastner
2006 Lecture Notes in Computer Science  
While processor based systems often enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable hardware typically offer no such protection  ...  Our approach includes a specialized compiler that translates a policy of legal sharing to reconfigurable logic blocks which can be directly transferred to an FPGA.  ...  Through the use of a grammar we allow the hierarchical composition of more complex policies.  ... 
doi:10.1007/11863908_28 fatcat:4ruhyhl25bb5rddk5c3fap6zai

Development and validation of Nessie: a multi-criteria performance estimation tool for SoC

Alienor Richard, Cedric Hernalsteens, Frederic Robert
2009 2009 Ph.D. Research in Microelectronics and Electronics  
We successively present the modeling of these primitives and the way the solutions are defined and explored based on the power criterion further in Section.  ...  The system compiler then automatically maps the application onto the platform and generates the application code and a system model that can be used for virtual prototyping.  ...  Rapid prototyping is enabled by the use of FPGA that is mostly used for SW development and system analysis.  ... 
doi:10.1109/rme.2009.5201349 fatcat:lk2x6luvzzfopl24okg723lfhu

Level 3 trigger algorithm and Hardware Platform for the HADES experiment

Daniel Georg Kirschner, Geydar Agakishiev, Ming Liu, Tiago Perez, Wolfgang Kühn, Vladimir Pechenov, Stefano Spataro
2009 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
Das GE-MN System besitzt zwei Gigabit-Ethernet Schnittstellen für den Transport von Daten, eine VMEbus Schnittstelle zur Konguration und Überwachung sowie einen TigerSHARC DSP zur Datenverarbeitung.  ...  As usual, the Einstein-convention is used, omitting the summation symbol in the formula whenever a index happens to appear twice in the same term.  ...  This data path is also used for most low level debugging, as well as to boot the DSP.  ... 
doi:10.1016/j.nima.2008.09.054 fatcat:qbg3huhmhjdufic7voggmqys4i

A Fault-tolerance Linguistic Structure for Distributed Applications [article]

Vincenzo De Florio
2016 arXiv   pre-print
A first contribution of this dissertation is the definition of a base of structural attributes with which application-level fault-tolerance structures can be qualitatively assessed and compared with each  ...  This result is then used to provide an elaborated survey of the state-of-the-art of software fault-tolerance structures.  ...  ACKNOWLEDGEMENTS This work would not have been possible without the contributions of a number of people who have supported me throughout these years. I thank very much my promoter, Prof. R.  ... 
arXiv:1611.01690v1 fatcat:mtyx6ubjafhzter5zream33d5u

Enforcing memory policy specifications in reconfigurable hardware

Ted Huffmire, Timothy Sherwood, Ryan Kastner, Timothy Levin
2008 Computers & security  
While general-purpose processor based systems are built to enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable hardware typically  ...  We also describe a technique for ensuring that the internal state of the reference monitor cannot be used as a covert storage channel.  ...  Through the use of a grammar we allow the hierarchical composition of more complex policies.  ... 
doi:10.1016/j.cose.2008.05.002 fatcat:krgulshf7fdhrmvfls4y3566yq
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