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System design validation using formal models

P. Henderson, R. Walters
Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)  
Using a model will not provide proof of the system, but it can help to find shortcomings and errors at an early stage.  ...  We show how a formal model can be sympathetic to this type of architecture using our tool, RolEnact and explain how this may be related to a COM implementation.  ...  Hence, we propose that a reasonable alternative is to build an abstract model of the system using a formal modelling tool.  ... 
doi:10.1109/iwrsp.1999.779024 dblp:conf/rsp/HendersonW99 fatcat:hj4qmgjby5awbghixgtgvoigwi

Design validation of embedded dependable systems

A. Bondavalli, A. Fantechi, D. Latella, L. Simoncini
2001 IEEE Micro  
Many application fields use computer-controlled systems, with different levels of criticality requirements.  ...  Usual design practices often suffer from partial approaches, overlooked details, inadequate modeling, insufficient prototyping, and limited design tools or available techniques.  ...  Formal verification The Guard project used formal approaches for specification and as a design aid.  ... 
doi:10.1109/40.958699 fatcat:wghik64werc27lhq3tyumg2xn4

Using Formal Methods to Model a Smart School System via TLA+ and its TLC Model Checker for Validation

Nawar Obeidat, Carla Purdy
2021 Advances in Science, Technology and Engineering Systems  
In this paper, we have used UML diagrams and the formal specification language TLA+ to design a smart school building system. We validate our design using the TLC model checker.  ...  Our contribution to this work is in focusing on using formal methods to prove that a design model meets its specifications.  ...  Acknowledgment Figure 2 and Figure 4 were made using chart-making tools at www.lucidchart.com and the authors would like to thank the website.  ... 
doi:10.25046/aj060295 fatcat:xp2jh2horvgj5hwy7ihvpgc7ri

Formal Verification Of Cache System Using A Novel Cache Memory Model

Guowei Hou, Lixin Yu, Wei Zhuang, Hui Qin, Xue Yang
2015 Zenodo  
verification is presented for such system design.  ...  For cache system contains data cache (Dcache) and instruction cache (Icache), Dcache memory model and Icache memory model are established separately using the same mechanism.  ...  Formal verification use mathematics to validate that the RTL design is consonant with design intention specification. Formal verification methods do not require test benches or vectors.  ... 
doi:10.5281/zenodo.1099783 fatcat:uwjpsnfc65eghmjeryukl7px7y

Design for validation

S.C. Johnson, R.W. Butler
1992 IEEE Aerospace and Electronic Systems Magazine  
The use of computer hardware and software in lifecritical applications, such as for civil air transports, demands the use of rigorous formal mathematical validation procedures.  ...  This paper presents a design methodology based on the concept of designing a system in such a manner that it can be rigorously validated, or design for validation."  ...  The Design-for-Validation Methodology System design begins with a detailed description of the system requirements written in a formal, mathematical language.  ... 
doi:10.1109/62.127129 fatcat:hprm3fravfdjrbkovd4mbrnlt4

Analyze the Mode Transition Logic of Automatic Flight Control System using Semi-Formal Approach

Rathina Kumar V, Nanda M
2016 Journal of Aeronautics & Aerospace Engineering  
Similar semiformal based approach can be used to reduce the design effort in the design and development of complex system designs as compared to the manual analysis.  ...  The MTL is analyzed and validated for its correct, complete, and reliable functionality and operation using Stateflow.  ...  MTL Model Design Validation MTL model design validation was done at the model level, code level and cross validated using third party tool.  ... 
doi:10.4172/2168-9792.1000167 fatcat:zkf6duf36jdn5pwhpwyyqobjiq

Formal techniques for SystemC verification

Moshe Y. Vardi
2007 Proceedings - Design Automation Conference  
By formal techniques we refer here to a range of techniques, including assertion-based dynamic validation, symbolic simulation, formal test generation, explicit-state model checking, and symbolic model  ...  While a major goal of SystemC is to enable verification at higher level of abstraction, enabling early exploration of system-level designs, the focus so far has been on traditional dynamic validation techniques  ...  FORMAL TECHNIQUES FOR SYSTEMC MODELS While a major goal of SystemC is to enable modeling and verification at higher level of abstraction, enabling early exploration of system-level designs, the focus in  ... 
doi:10.1145/1278480.1278527 dblp:conf/dac/Vardi07 fatcat:pucrpnf2kngmrmmvi64rg65gki

Verification and Validation of Behavior Models Using Lightweight Formal Methods [chapter]

Kristin Giammarco, Kathleen Giles
2017 Disciplinary Convergence in Systems Engineering Research  
The research described herein provides a method for exposing invalid behaviors in systems of systems (SoS) early in design, at the architecture level.  ...  Examples from four models from different domains and developed by different students are presented, then used as a basis for developing a structured set of behavior model V&V criteria that may be applied  ...  Acknowledgments The Consortium for Robotics and Unmanned Systems Education and Research (CRUSER) sponsored the development of the MP analyzer tool that enabled all of the student models and their discoveries  ... 
doi:10.1007/978-3-319-62217-0_31 fatcat:45cxcl6prrdpxbykyp2djcwiue

The challenge of interoperability

Huafeng Yu, Prachi Joshi, Jean-Pierre Talpin, Sandeep Shukla, Shinichi Shiraishi
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
A novel model-based formal integration framework is being developed to enable architecture modeling, timing specification, formal semantics, design by contract and optimization in the system-level design  ...  However, heterogeneity, interoperability, and the lack of formal semantic underpinning in modeling, integration, validation and optimization make design automation a big challenge, which becomes a hindrance  ...  design complexity and validation time.  ... 
doi:10.1145/2744769.2747945 dblp:conf/dac/YuJTSS15 fatcat:dlsu7o7t4bgebgx7bv4wrlk7z4

Property Model Methodology: A Landing Gear Operational Use Case

Patrice Micouin, Louis Fabre, Roland Becquet, Pascal Paper, Thomas Razafimahefa, François Guérin
2018 INCOSE International Symposium  
subsystems detailed designs (4) Validating the requirements specified to the contributing subsystems by proof or simulation, (5) Verifying the design models by simulation and finally (6-8) Verifying physical  ...  and simulation, (3) Modeling the architectural design, Refining the top level requirements into requirements specified to the different subsystems contributing to the function and Modeling the terminal  ...  Step 2: Specification Formal and Factual Validation, a formal validation of the system specification model is performed in order to complete it and to remove contradictions.  ... 
doi:10.1002/j.2334-5837.2018.00484.x fatcat:cpdyby7id5eb7ctwfamrqxooky

The application of PROMELA and SPIN in the BOS project [chapter]

Pim Kars
1997 The SPIN Verification System  
of validation.  ...  After a short introduction to the BOS project, we discuss the \why, what and how" of the use of formal methods in the project, some recent experience using Promela/Spin and re ections on the pragmatics  ...  Formalization of the design It may be useful to rst indicate the kind of systems we h a ve experience with.  ... 
doi:10.1090/dimacs/032/05 dblp:conf/dimacs/Kars96 fatcat:cfkjiu3ynzd6ljqa2t6rscsh3m

Refinement: A Constructive Approach to Formal Software Design for a Secure e-voting Interface

Dominique Cansell, J. Paul Gibson, Dominique Méry
2007 Electronical Notes in Theoretical Computer Science  
Using the B-method, we apply an incremental refinement approach to verifying a sequence of designs of the interface for the collection and storage of votes, which we prove to be correct with respect to  ...  We demonstrate that an incorrect interface is a major security threat and show the use of the formal method B in guaranteeing simple safety properties of the voting interface of a voting machine implementing  ...  more formal model-checking or theoremproving can be used to show that the design is correct.  ... 
doi:10.1016/j.entcs.2007.01.060 fatcat:4vkkhswwrjdmtoyajlkk6rltvm

Scenario-based validation of embedded systems

A. Gargantini, E. Riccobene, P. Scandurra, A. Carioni
2008 2008 Forum on Specification, Verification and Design Languages  
This paper describes a scenario-based methodology for system-level design validation based on the Abstract State Machines formal method.  ...  It allows the designer to functionally validate system components from SystemC UML designs early at high levels of abstraction and without requiring strong skills and expertise on formal methods.  ...  Conclusions and future work We proposed a scenario-based validation approach to system-level design by the use of the SystemC UML profile (for the modelling part) and the ASM formal method and its related  ... 
doi:10.1109/fdl.2008.4641444 dblp:conf/fdl/GargantiniRSC08 fatcat:f3dpsufljbbkxby32mxrq4463i

MBSE and V&V: a tool-equipped method for combining various V&V strategies

B. Nastov, V. Chapurlat, F. Pfister, C. Dony
2017 IFAC-PapersOnLine  
Abstract: Model-Based System engineering (MBSE) promotes Verification and Validation (V&V) as crucial activities to demonstrate, during the system design stage and based on models, that a system meets  ...  Abstract: Model-Based System engineering (MBSE) promotes Verification and Validation (V&V) as crucial activities to demonstrate, during the system design stage and based on models, that a system meets  ...  System Engineering and Model Driven principles, Model-Based Systems Engineering (MBSE) is defined as the formalized application of modeling to support system requirements, design, analysis, verification  ... 
doi:10.1016/j.ifacol.2017.08.1309 fatcat:5npryo7qm5d2venpjjbenjcn3q

Formal aspects of model validity and validation in system dynamics

Yaman Barlas
1996 System Dynamics Review  
The challenge is to design formal/quantitative validation procedures and tests suitable for system dynamics models, while keeping the above philosophical perspective.  ...  The challenge is to design formal/quantitative validation procedures and tests suitable for system dynamics models, while keeping the above philosophical perspective.  ... 
doi:10.1002/(sici)1099-1727(199623)12:3<183::aid-sdr103>3.0.co;2-4 fatcat:7lkqio52vfhspcgcqkpuozkpcu
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