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Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA

T. Arpinen, T. Koskinen, E. Salminen, T.D. Hamalainen, M. Hannikainen
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
This paper presents how UML2 models of IP-XACT features can be utilized to efficiently design and implement a multiprocessor SoC prototype on FPGA.  ...  Despite the number of proposals at conceptual level, experiences on utilizing this representation in practical SoC development environments are very limited.  ...  The first approach was to write the top-level VHDL file according to a given specification without any automation.  ... 
doi:10.1109/date.2009.5090665 dblp:conf/date/ArpinenKSHH09 fatcat:vyr3l3o7izgx5bq4nezlqksqma

Application of design patterns for hardware design

Robertas Damaševičius, Giedrius Majauskas, Vytautas Štuikys
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We propose a Wrapper design pattern for adapting the behavior of the soft IPs, and demonstrate its application to the communication interface synthesis.  ...  Design patterns, which encapsulate common solutions to the recurring design problems, have contributed to the increased reuse, quality and productivity in software design.  ...  The composition relationship describes the composition of a system from the components and corresponds to the VHDL port map statement.  ... 
doi:10.1145/775832.775847 dblp:conf/dac/DamaseviciusMS03 fatcat:sd2jgg6cmnghtj6xwmoe2s5xda

Extending UML for Electronic Systems Design: A Code Generation Perspective [chapter]

Yves Vanderperren, Wolfgang Mueller, Da He, Fabian Mischkalla, Wim Dehaene
2012 Design Technology for Heterogeneous Embedded Systems  
UML classes can be mapped onto VHDL entities, and associations between classes onto signals.  ...  Still, recent efforts such as [56] confirm that approaches based on a one-to-many mapping may gain maturity in the future and pave the road towards a unified design flow from specification to implementation  ...  The example also sketches how to write the code of an sc_module header and the opening and closing brackets into a file.  ... 
doi:10.1007/978-94-007-1125-9_2 fatcat:nkko7sivffe2pmtqg3s3sp52hy

Application of design patterns for hardware design

Robertas Damaševičius, Giedrius Majauskas, Vytautas Štuikys
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We propose a Wrapper design pattern for adapting the behavior of the soft IPs, and demonstrate its application to the communication interface synthesis.  ...  Design patterns, which encapsulate common solutions to the recurring design problems, have contributed to the increased reuse, quality and productivity in software design.  ...  The composition relationship describes the composition of a system from the components and corresponds to the VHDL port map statement.  ... 
doi:10.1145/775844.775847 fatcat:4egjlkuxibekvcgewn5qqy4pzq

System level modeling methodology of NoC design from UML-MARTE to VHDL

Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
2012 Design automation for embedded systems  
Our contribution includes a description of how these concepts may be mapped into VHDL. The generated code has been successfully evaluated and validated for several NoC topologies.  ...  Thus, there is a need for developing some automated high level modeling environments for computer aided design in order to handle the design complexity and meet tight time-to-market requirements.  ...  In [31] , an approach to map UML to VHDL is presented. It is based on a simple translation of UML concepts into VHDL ones.  ... 
doi:10.1007/s10617-012-9101-2 fatcat:h2l7x376tjfpdnqdblufmzvzmi

UML based hierarchical state diagram approach for protocol designs

Sreejith Sudhakaran, Wah Man Cheung, Klaus D. McDonald-Maier, Gareth Howells
2010 2010 2nd Computer Science and Electronic Engineering Conference (CEEC)  
This paper introduces a UML based visual design approach to address this increased complexity in the design of IP as well as Systemon-Chips (SoC).  ...  A Model Driven Development (MDD) method using UML state diagrams and hierarchical design breakdown approach is used for the development the synthesizable HDL for USB3.0 device IP with more than 20 sequential  ...  Another practice applied in this project is to use the hierarchical states in UML to represent complex state machines.  ... 
doi:10.1109/ceec.2010.5606496 fatcat:m3v3lfla5nbifnavexg2ighpwm

Formal Verification of Control Modules in Cyber-Physical Systems

Iwona Grobelna
2020 Sensors  
It also allows the early detection of any errors related to the specification. A case study of a manufacturing automation system is presented to illustrate the approach.  ...  The model is automatically transformed into a verifiable model in nuXmv format and into synthesizable code in VHDL language, which ensures that the resulting models are consistent with each other.  ...  A given initial abstract model is formally verified to reveal any property violations, then a mapping to a concrete model is determined, with validation of whether it is realistic or not.  ... 
doi:10.3390/s20185154 pmid:32927612 fatcat:4arojpav3ner7hv4v7n2f6q7ga

A Unified Approach to Code Generation from Behavioral Diagrams [chapter]

Dag Björklund, Johan Lilius, Ivan Porres
2004 Languages for System Specification  
We show two different approaches to code generation from UML behavioral models that are suitable for embedded systems.  ...  It can be used to uniformly describe the behavior of a combination of several diagrams and as a bridge from UML models to animation and production code.  ...  However, this approach requires, in order to be practical, that the produced code is so efficient that the programmer does not need to tweak it by hand.  ... 
doi:10.1007/1-4020-7991-5_2 dblp:conf/fdl/BjorklundLP03 fatcat:kgpglhylm5e6jewwggen6vvl2a

A computational independent model for a medical quality management information system

Evgeny A. Cherkashin, Ljubica Kazi, Alexey O. Shigarov, Viacheslav V. Paramonov
2018 Scientific-practical Workshop Information Technologies: Algorithms, Models, Systems  
QMS software subsystems are synthesized as a result of a logical inference of a set of subgoals (a scenario) with a hierarchy of modules represented in the LogTalk programming language within Model Driven  ...  The system is intended to organize the process management of medical treatment according to the standard ISO 9001:2015.  ...  Code generation is done on the basis of a set of well-defined mapping rules between SysML and VHDL concepts.  ... 
dblp:conf/itams/CherkashinKSP18 fatcat:qnzjf426cvhive5c2l5uwx7nw4

Automatic SystemC Code Generation from UML Models at Early Stages of Systems on Chip Design

Fateh Boutekkouk
2010 International Journal of Computer Applications  
In the first level, we use UML hierarchic sequence diagrams to generate a SystemC code that targets algorithmic space exploration and simulation.  ...  In this paper, we present our approach for automatic SystemC code generation from UML models at early stages of Systems On Chip (SOC) design.  ...  However, there is a lack of tools that can synthesize UML models into SLL descriptions.  ... 
doi:10.5120/1215-1744 fatcat:up7nymph2zedrjjyihvmx7hmnq

Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study

Jorn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, Mickael Raulet
2008 2008 IEEE Workshop on Signal Processing Systems  
Concerning the C code generator results, the results show that the synthesized C-software mapped on a SystemC scheduler platform, is much faster than the simulated CAL dataflow program and approaches handwritten  ...  This paper presents a new framework which allows the specification, design, simulation and implementation of a system operating at a higher level of abstraction compared to current approaches.  ...  UML models (i.e. application, platform and mapping models) are written according to the experience of the designers. However, there is limited support for the elaboration of UML specifications.  ... 
doi:10.1109/sips.2008.4671777 dblp:conf/sips/JanneckMPRWR08 fatcat:ev5nhvqmunauzhjveqbzke2ehq

Model-driven automation for simulation-based functional verification

Éamonn Linehan, Eamonn O'Toole, Siobhán Clarke
2012 ACM Transactions on Design Automation of Electronic Systems  
Developing testbenches for dynamic functional verification of hardware designs is a software intensive process that lies on the critical path of electronic system design.  ...  The increasing capabilities of electronic components is contributing to the construction of complex verification environments that are increasingly difficult to understand, maintain, extend and reuse across  ...  We also thank Aurélien Mariage, INSA Toulouse for his contribution to the development of many of the tools presented in the paper.  ... 
doi:10.1145/2209291.2209304 fatcat:q2f46ctjjnbmldyuagb4xw43fa

Formal ESL Synthesis for Control-Intensive Applications

Michael F. Dossis
2012 Advances in Software Engineering  
Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process.  ...  Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to  ...  In practice, the authors found this approach to deliver quality-of-results and performance improvements, even compared with a very fast constructive floorplanner.  ... 
doi:10.1155/2012/156907 fatcat:f55w3dv6crflzfqinksfrcahnu

The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems

Fernando Herrera, Héctor Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia, Gianluca Palermo
2014 Journal of systems architecture  
This paper presents the COMPLEX UML/MARTE Design Space Exploration methodology, an approach based on a novel combination of Model Driven Engineering (MDE), Electronic System Level (ESL) and design exploration  ...  The proposed framework enables capturing the set of possible design solutions, that is, the design space, in an abstract, standard and graphical way by relying on UML and the standard MARTE profile.  ...  .,); and supports a generic, RTOS independent API, which enables the analysis of different architectural mappings without the need to generate the complete SW stack in each executing node or to synthesize  ... 
doi:10.1016/j.sysarc.2013.10.003 fatcat:5k5qgkqna5cznjqrrzqznvnixy

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia (+2 others)
2013 Microprocessors and microsystems  
Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific  ...  Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies.  ...  [13] proposes an interesting approach to power efficient system design using UML generated executable models.  ... 
doi:10.1016/j.micpro.2013.09.001 fatcat:7a5ycc45m5h7nkjhxhe4u2j7am
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