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Synthesizable High Level Hardware Descriptions

Jennifer Gillenwater, Gregory Malecha, Cherif Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O'leary
2010 New generation computing  
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog.  ...  These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable.  ...  VPP statically checks the synthesizability of a Verilog description (possibly containing high level abstractions) and elaborates it if it is well-typed (Section 6).  ... 
doi:10.1007/s00354-008-0093-1 fatcat:oznuzav3vbfzhdk3vvwybrvyiy

Synthesizable high level hardware descriptions

Jennifer Gillenwater, Gregory Malecha, Cherif Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O'Leary
2008 Proceedings of the 2008 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation - PEPM '08  
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog.  ...  These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable.  ...  VPP statically checks the synthesizability of a Verilog description (possibly containing high level abstractions) and elaborates it if it is well-typed (Section 6).  ... 
doi:10.1145/1328408.1328416 dblp:conf/pepm/GillenwaterMSZTGO08 fatcat:nx3n4yx5m5akjcjjv77apm5h3a

Automatic generation of synthesizable hardware implementation from high level RVC-cal description

Khaled Jerbi, Mickael Raulet, Olivier Deforges, Mohamed Abid
2012 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
Before the modifications presented in this paper, the existing CAL hardware back-end did not support some high-level features of the CAL language.  ...  In our work we adopted a high level and target-independent language called CAL (Caltrop Actor Language).  ...  to low level description.  ... 
doi:10.1109/icassp.2012.6288199 dblp:conf/icassp/JerbiRDA12 fatcat:gasym5wzg5dz7idah6nns5oqqu

Hardware synthesis from C/C++

Abhijit Ghosh, Joachim Kunkel, Stan Liao
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
With these enhancements, it is possible to create C/C++ descriptions of hardware at the well-understood RTL and behavioral levels of abstraction, providing an opportunity to leverage existing, mature hardware-synthesis  ...  Also, a synthesizable subset of the language needs to be defined, together with synthesis semantics for programming language constructs.  ...  Secondly, C/C++ provides capabilities that are beyond traditional HDL, allowing compact descriptions at a high level of abstraction.  ... 
doi:10.1145/307418.307529 fatcat:q62sbxrk6vcvznls5m4da2ckcm

Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms [chapter]

Klaas L. Hofstra, Sabih H. Gerez
2007 Lecture Notes in Computer Science  
This calls for hardware description formalisms targeted for efficient simulation (such as the programming language C).  ...  This resulted in Arx, which is meant for signal-processing hardware at the register-transfer level, either using floating-point or fixed-point data.  ...  The Workflow The Arx language and toolset enable a stepwise refinement design methodology that starts with a high-level description and iteratively reaches an optimized synthesizable description.  ... 
doi:10.1007/978-3-540-69338-3_15 fatcat:3wxb6tjbzre2he2s3yrvgy3zi4

Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs

Qilin Si, Santosh Shetty, Benjamin Carrion Schaefer
2021 Electronics  
High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems.  ...  This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of  ...  Bus Type master.v master_IF.v bus.v slave_IF.v slave.v master.IFF bus.IFF slave_IF.IFF master_IF.IFF slave.IFF High-Level Synthesis (Allocation, Scheduling, Binding) Bus High-Level Synthesis  ... 
doi:10.3390/electronics10141746 fatcat:roigcuzeyve2rl24btmahnczcu

An overview of a compiler for mapping MATLAB programs onto FPGAs

P. Banerjee
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
The MATCH compiler reads in high-level descriptions of DSP applications written in MATLAB, and automatically generates synthesizable RTL models in VHDL.  ...  The paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer.  ...  Related Work The problem of translating a high-level or behavioral language description into a register transfer level representation is called high-level synthesis [6] .  ... 
doi:10.1145/1119772.1119870 dblp:conf/aspdac/Banerjee03 fatcat:6dr3pokj4zhuhpza24tgjikwum

Accelerating System Verilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator

Abhishek Jain, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar
2013 International Journal of VLSI Design & Communication Systems  
components between the software simulator and hardware accelerator respectively.  ...  This paper covers development of Acceleratable UVCs from standard UVCs for internal control and data buses of ST imaging group by partitioning of transaction-level components and cycle-accurate signal-level  ...  Models described using high-level language (HVL) constructs are executed by the simulator and the models described using hardware description language (HDL) constructs are executed by the hardware accelerator  ... 
doi:10.5121/vlsic.2013.4602 fatcat:f5gfwr4sxzazjl6zsqnx54skpi

Electronic System Design Automation Using High Level Petri Nets [chapter]

Patrik Rokyta, Wolfgang Fengler, Thorsten Hummel
2000 Hardware Design and Petri Nets  
A design and implementation methodology for system specification, modelling and implementation using a special kind of high level Petri nets is described.  ...  Electronic system design automation tools are used to generate synthesizable VHDL code from a Petri net model.  ...  These hardware description languages can be synthesized to a gatelevel netlist.  ... 
doi:10.1007/978-1-4757-3143-9_10 fatcat:shphzfletrce7jghxoful2tmly

Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters

L. Laguna, R. Prieto, J. Oliver, J. Cobos
2008 2008 11th IEEE International Power Electronics Congress  
This paper presents a research line oriented to develop methodologies that takes advantage of hardware description languages in order to simplify the design of power converters that employ digital control  ...  actual electric + synthesizable code).  ...  In hardware description languages it is possible to define sub-tests for a given model.  ... 
doi:10.1109/ciep.2008.4653827 fatcat:3axh7wu3urcrla5juk46docdmq

Fast Hardware Implementation of an Hadamard Transform Using RVC-CAL Dataflow Programming

Khaled Jerbi, Matthieu Wipliez, Mickael Raulet, Olivier Deforges, Marie Babel, Mohamed Abid
2010 2010 5th International Conference on Embedded and Multimedia Computing  
The algorithm, typically described in a high-level specification language, must be translated to a low-level HDL language.  ...  This paper presents a global design method going from high level description to implementation. The first step consists in describing an algorithm as a dataflow program with the RVC-CAL language.  ...  Currently, high-level RVC-CAL descriptions must be manually transformed to lower-level code for Cal2HDL to be able to synthesize it.  ... 
doi:10.1109/emc.2010.5575731 fatcat:fl6uwhfx4fhdnpu2l6bhztgzjm

Python as a hardware description language: A case study

J.I. Villar, J. Juan, M.J. Bellido, J. Viejo, D. Guerrero, J. Decaluwe
2011 2011 VII Southern Conference on Programmable Logic (SPL)  
However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages.  ...  Many people may see the development of software and hardware like different disciplines.  ...  Verilog and VHDL Code Generation As in other hardware description languages, the generation of synthesizable code in MyHDL has several limitations.  ... 
doi:10.1109/spl.2011.5782635 fatcat:fsxlwurkjbdidoyio6audtjktm

Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2009 Journal of Information Processing  
This paper proposes CHStone, a suite of benchmark programs for C-based high-level synthesis.  ...  In addition, we present future challenges to be solved towards the practical high-level synthesis.  ...  This paper proposed CHStone, a suite of benchmark programs for C-based high-level synthesis.  ... 
doi:10.2197/ipsjjip.17.242 fatcat:xvy6zld54nghdhjvkrrrf3vugu

Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure

Bill Jason Tomas, Yingtao Jiang, Mei Yang
2014 International Journal of Computer Science & Information Technology (IJCSIT)  
A high-level (SystemC) testbench and FPGA synthesizable hardware transactor models are developed for the ISCAS89 S400 benchmark circuit for high-speed communication between the CPU workstation and FPGA  ...  Verification teams have adopted emulation as a prominent methodology, incorporating high-level testbenches and FPGA/ASIC hardware for system-level testing (SLT).  ...  Designer engineers utilize hardware description languages (HDL) to characterize the system on the RTL level, to be able to observe signal data between synchronous elements.  ... 
doi:10.5121/ijcsit.2014.6406 fatcat:ryxoy6fasfax3nsvrbnxca6e4e

Transformational System Design Based on Formal Computational Model and Skeletons [chapter]

Wenbiao Wu, Ingo Sander, Axel Jantsch
2001 System-on-Chip Methodologies & Design Languages  
The Formal System Design methodology ForSyDe [1, 2, 3] is extended by a systematic refinement methodology based on transformations, which gradually transforms a high-level, function oriented system description  ...  into a synthesizable model.  ...  transforming this into a description at a lower level, possibly in a hardware description language.  ... 
doi:10.1007/978-1-4757-3281-8_15 fatcat:v34ycqmbr5cn5cgoofawm4i65e
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